Photoluminescence spectroscopy is one of the most efficient and sensitive non-contact techniques used to investigate defects in SiC. In this work, room temperature photoluminescence mapping is employed to identify different defects that influence material properties. The correlation of the distribution of these defects in n-type 4H-SiC substrates with electronic properties of SiC revealed connection between the deep levels acting as efficient recombination centers and doping in the substrate. Since deep levels are known to act as minority carrier lifetime killers, the obtained knowledge may contribute to our ability to control important characteristics such as minority carrier lifetime in SiC. In semi-insulating (SI) 6H-SiC, the correlation between room temperature infrared photoluminescence maps and the resistivity maps is used to identify deep defects responsible for semi-insulating behavior of the material. Different defects were found to be important in different families of SI SiC substrates, with often more than one type of defect playing a significant role. The obtained knowledge is expected to enhance the yield of SI SiC fabrication and the homogeneity of the resistivity distribution across the area of large SiC substrates.

Předkládaná práce se zabývá parametrem “Reverse Recovery Time“ u polovodičových prvků a jeho vlivem na typické spínací obvody. V první části práce je objasněno co je “Reverse Recovery Time“ a jeho jednotlivé části. V další sekci je popsána jeho fyzikální podstata. Na konci teoretická části je rozebrán jeho efekt na spínací ztráty a doporučená metoda měření tohto parametru . Praktická část práce je zaměřena na simulace Dpdr45nres45 v prostředích Cadence a TCAD. Poslední část se zabývá návrhem obvodu na měření u reálných diod a samotným měřením diod a tranzistorů.

CdTe an II-VI semiconductor has been a leading thin film photovoltaic material due to its near ideal bandgap and high absorption coefficient [1]. The typical thin film CdTe solar cells have been of the superstrate configuration with CdS (Eg-2.42eV) as the n-type heterojunction partner. Due to the relatively narrow bandgap of CdS, a wider bandgap n-type window layer has recently emerged as a promising substitute: alloys of MgyZn1-yO have been successfully used as the emitter or window layer. The benefits in the usage of MgyZn1-yO (MZO) are its tunable bandgap and wide optical spectrum on optoelectronic devices. Due to an increasing bandgap of the window layer, the carrier collection can be improved in the short wavelength range (<500 nm). In addition alloys of CdSexTe1-x (CST) have also been used in the absorber layer (i.e., CST/CdTe) for the fabrication of CdTe devices to improve the carrier collection and lifetime [2]. The lower bandgap of the CST alloy can lead to higher short-circuit current (JSC), but it can also result in lower open circuit voltage (VOC). Another critical aspect of the CdTe solar cell is the use of copper as a p-type dopant, which is typically incorporated in the cell during the fabrication of the back contact. The most challenging issue related to further advancing the CdTe solar cell efficiency is the relatively low level of p-type doping, which limits the VOC. Efforts to dope CdTe with group V dopants are yet to produce the desired results. ZnO has been used as an effective high resistivity transparent. When CdTe is deposited directly on sputtered ZnO, VOC of typically 500-600 mV is produced. Band alignment measurements indicate that a negative conduction band offset with CdS exists; alloying with MgO to produce MgyZn1-yO with a composition of y = 0.15 can produce a flat conduction band alignment with CdS. This material has an additional benefit for improving the energy bandgap of the MZO for better UV light transmission in the short wavelengths. By changing the magnesium content from y = 0 to 0.30 allowed researchers to make the tunable conduction band offset from a “cliff” to a “spike,” with both increased open-circuit voltage and fill factor as increasing magnesium compositions [3] — the bandgap gains as expected with increased magnesium composition. The large compositions (y > 0.30) of MgyZn1-yO cause the enormous spike result in S-kink in the IV measurement so that the FF decreases. Besides, due to the instability of MZO material, the fabrication process has to proceed carefully. The properties of CST films and cells were investigated as a function of Se composition (x), substrate temperature (TSUB), and ambient used during the CSS deposition. The higher ratio of Se in CST alloy causes the smaller grain structures and lower bandgap, which profoundly detrimental to the device performance (VOC). However, the CST can be deposited in various substrate temperatures and different inert ambient gas to improve the grain structure by utilizing the especial Close Space Sublimation (CSS) deposition system. Therefore, despite the fact that the CST (25% Se) has the optical bandgap (1.37eV), the improvement of grain structure can slightly increase the doping concentration and decrease the grain boundary (GBs) due to increased alloys grain size 3X larger, which is contributed to improving the VOC [4]. The study of higher ratio Se of CST alloy is significant to achieve the high efficiency polycrystalline CST/CdTe photovoltaic devices. The effect of Cu doping back contact in CdSexTe1-x (CST)/CdTe solar cells with varying amounts of Se (x) has been investigated. The Cu-based back contact was annealed at different thermal temperatures in order to vary the amount of Cu in-diffusion. Net p-type doping was found to increase as the back-contact annealing temperature increased. All cells exhibited a decrease in VOC with increased annealing temperature (i.e., higher Cu concertation), presumably due to a degradation of the lifetime with increased amounts of Cu [5]. However, cells with the highest Se composition appeared to exhibit a higher degree of tolerance to the amount of Cu – i.e., they exhibited a smaller loss in VOC with the increased amount of Cu. Extrinsic p-type doping of CdSeTe can be fabricated using two different experimental processes. Firstly, by using group I elements such as, Cu to substitute Cd, which is promising during the back contact process. Secondly, using group V (P, As, Sb) elements to substitute Te, and this is suitable for Cd-rich of intrinsic CdTe. Intrinsic CST alloy has lower hole density concentration as higher Se composition with limitation of the VOC. Thus, in order to increase the p-type net doping up to 1016 cm-3 the extrinsic P or As doping have been widely investigated recently. The research studies show the CST/CdTe devices lead to improve VOC up to 850 mV with higher hole density in higher Se compositions of As doped CST alloys. Nevertheless, the group V doped CdTe still cause the formation of compensating defects limits the upper boundary of dupability on the CdTe thin film solar cells. Even if a high hole density concentration is achieved for intrinsically-doped p-type CST/CdTe, it is believed the poor carrier lifetime in the CdTe side would still limit the VOC.

Minority carrier transport properties and the effects of electron irradiation/injection were studied in GaN and ZnO containing dopants known to form acceptor states deep within the materials' bandgap. Minority carrier diffusion length and lifetime changes were investigated using Electron Beam Induced Current (EBIC) method, cathodoluminescence spectroscopy, spectral photoresponse and persistent photoconductivity measurements. It is shown that electron irradiation by the beam of a scanning electron microscope results in a significant increase of minority carrier diffusion length. These findings are supported by the cathodoluminescence measurements that demonstrate the decay of near-band-edge intensity as a consequence of increasing carrier lifetime under continuous irradiation by the electron beam. Temperature-dependent measurements were used to determine the activation energies for the electron irradiation-induced effects. The latter energies were found to be consistent with the involvement of deep acceptor states. Based on these findings, the effects of electron irradiation are explained via the mechanism involving carrier trapping on these levels. Solid-state electron injection was also shown to result in a similar increase of minority carrier lifetime and diffusion length. Solid-state injection was carried out by applying the forward bias to a ZnO homojunction and resulted in a significant improvement of the peak photoresponse of the junction. This improvement was unambiguously correlated with the increase of the minority carrier diffusion length due to electron injection.

No description available.

The Cadmium Telluride thin film solar cell is one of the leading photovoltaic technologies. Efficiency improvements in the past decade made it a very attractive and practical source of renewable energy. Considering the theoretical limit, there is still room for improvement, especially the cell’s open circuit voltage (VOC). To improve VOC, the p-type carrier concentration and minority carrier lifetime of the CdTe absorber needs to be improved. Both these parameters are directly related to the point defect distribution of the semiconductor, which is a function of deposition stoichiometry, dopant incorporation and post-deposition treatments. CdTe films were deposited by the Elemental Vapor Transport (EVT) deposition method, which allowed in situ control of the vapor phase stoichiometry (Cd/Te ratio). Extrinsic doping of polycrystalline CdTe by in situ incorporation of antimony (Sb) and phosphorus (P) was investigated. The structural and electrical properties of CdTe thin films and solar cells were studied. Sb and P incorporation were found to increase the net p-doping concentration. Cl and Sb improved the minority carrier lifetime of polycrystalline CdTe, while lower lifetime with Cu and P doped films were indicated. Deep Level Transient Spectroscopy (DLTS) was performed on devices fabricated with different deposition stoichiometry, post-deposition treatments, and phosphorus dopant dose. Several majority and minority carrier traps were identified, and assigned to different point defects based on first principle studies in the literature and experimental conditions used for the deposition and processing of the thin films.

abstract: It has been a long-standing goal to epitaxially integrate III-V alloys with Si substrates which can enable low-cost microelectronic and optoelectronic systems. Among the III-V alloys, gallium phosphide (GaP) is a strong candidate, especially for solar cells applications. Gallium phosphide with small lattice mismatch (~0.4%) to Si enables coherent/pseudomorphic epitaxial growth with little crystalline defect creation. The band offset between Si and GaP suggests that GaP can function as an electron-selective contact, and it has been theoretically shown that GaP/Si integrated solar cells have the potential to overcome the limitations of common a-Si based heterojunction (SHJ) solar cells. Despite the promising potential of GaP/Si heterojunction solar cells, there are two main obstacles to realize high performance photovoltaic devices from this structure. First, the growth of the polar material (GaP) on the non-polar material (Si) is a challenge in how to suppress the formation of structural defects, such as anti-phase domains (APD). Further, it is widely observed that the minority-carrier lifetime of the Si substrates is significantly decreased during epitaxially growth of GaP on Si. In this dissertation, two different GaP growth methods were compared and analyzed, including migration-enhanced epitaxy (MEE) and traditional molecular beam epitaxy (MBE). High quality GaP can be realized on precisely oriented (001) Si substrates by MBE growth, and the investigation of structural defect creation in the GaP/Si epitaxial structures was conducted using high resolution X-ray diffraction (HRXRD) and high resolution transmission electron microscopy (HRTEM). The mechanisms responsible for lifetime degradation were further investigated, and it was found that external fast diffusors are the origin for the degradation. Two practical approaches including the use of both a SiNx diffusion barrier layer and P-diffused layers, to suppress the Si minority-carrier lifetime degradation during GaP epitaxial growth on Si by MBE were proposed. To achieve high performance of GaP/Si solar cells, different GaP/Si structures were designed, fabricated and compared, including GaP as a hetero-emitter, GaP as a heterojunction on the rear side, inserting passivation membrane layers at the GaP/Si interface, and GaP/wet-oxide functioning as a passivation contact. A designed of a-Si free carrier-selective contact MoOx/Si/GaP solar cells demonstrated 14.1% power conversion efficiency. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

This work presents a summary of experimental data and theoretical models that characterize the temperature-dependent behavior of key carrier-transport parameters in silicon down to cryogenic temperatures. In extreme environment applications such as space-based electronics, accurate models of carrier recombination, carrier mobility, and incomplete ionization of dopants form a necessary foundation for the development of reliable high-performance devices and circuits. Not only do these models have a wide impact on the simulated DC and AC performance of devices, but they also play a critical role in predicting the behavior of important phenomena such as single event upset in digital logic circuits. With this motivation, an overview is given of SRH recombination theory, addressing in particular the dependence of recombination lifetime on temperature and injection level. Carrier lifetime measurement methods are reviewed, and experiments to study carrier lifetimes in the substrate of a commercial SiGe BiCMOS process are presented. The experimental data is analyzed and leveraged in order to develop calibrated TCAD-relevant models. Similarly, an overview of low-temperature resistivity in silicon is presented. Modeling of resistivity over temperature is discussed, addressing the prevailing theoretical models for both carrier mobility and incomplete ionization of dopants. Experimental measurements of the temperature dependence of resistivity in both p-type and n-type silicon are presented, and calibrated TCAD-relevant models for carrier mobility and incomplete ionization are developed. Finally, the ability to integrate these calibrated models within commercial TCAD software is demonstrated. In addition, applications for these accurate temperature-dependent models are discussed, and future directions are outlined for research into cryogenic modeling of fundamental physical parameters.

This master´s thesis deals with an examination of different solution types a for the chemical passivation of a silicon surface. Various solutions are tested on silicon wafers for their consequent comparison. The main purpose of this work is to find optimal solution, which suits the requirements of a time stability and start-up velocity of passivation, reproducibility of the measurements and a possibility of a perfect cleaning of a passivating solution remainig from a silicon surface, so that the parameters of a measured silicon wafer will not worsen and there will not be any contamination of the other wafers series in the production after a repetitive return of the measured wafer into the production process. The cleaning process itself is also a subject of a development.

Low cost, rapid and high thermal by IR heating, rapid cooling and high efficiency, there are RTP (Rapid Thermal Processing) properties. We can use RTP for annealing, diffusion, contacting, oxidation and others. Rapid temperature change and IR heating can be followed positive effects in the silicon substrate. This paper is focused on annealing by RTP. Wafers were p-type monocrystalline CZ silicon with different bulk minority carrier lifetime. Minority carrier lifetime was measured by MW-PCD (Microwave Photoconductance Decay) before and after thermal processing.