The growing demand for high performance systems in modern computing technology drives the development of advanced and high speed designs in I/O structures. Due to their data rate and architecture, however, testing of the high speed serial interfaces becomes more expensive when using conventional test methods. In order to alleviate the test cost issue, a loopback test scheme has been widely adopted. To assess the margin of the signal eye in the loopback configuration, the eye margin is purposely reduced by additional devices on the loopback path or using design for testability (DFT) features such as timing and voltage margining. Although the loopback test scheme successfully reduces the test cost by decoupling the dependency of external test equipment, it has robustness issues such as a fault masking issue and a non-ideality problem of margining circuits. The focus of this dissertation is to propose new methods to resolve the known issues in the loopback test mode. The fault masking issue in a loopback pair of analog to digital and digital to analog converters (ADC and DAC) which can be found in pulse amplitude modulation (PAM) signaling schemes is resolved using a proposed algorithm which separates the characteristics of the ADC and the DAC from a combined loopback response. The non-ideality problem of margining circuit is resolved using a proposed method which utilizes a random jitter injection technique. Using the injected random jitter, the jitter distribution is sampled by undersampling and margining, which provides the nonlinearity information using the proposed algorithm. Since the proposed method requires a random jitter source on the load board, an alternative solution is proposed which uses an intrinsic jitter profile and a sliding window search algorithm to characterize the nonlinearities. The sliding search algorithm was implemented in a low cost high volume manufacturing (HVM) tester to assess feasibility and validity of the proposed technique. The proposed methods are compatible with the existing loopback test scheme and require a minimal area and design overhead, hence they provide cost effective ways to enhance the robustness of the loopback test scheme. / text

The proliferation of wireless communication devices in the recent past has increased the pressure on semiconductor manufacturers to produce quality radio frequency (RF) modules and systems at a low cost. This entails reducing their test cost as well, since the cost of testing modern RF devices can be up to 40% of their manufacturing cost. The high test cost of these devices can be mainly attributed to (a) the expensive nature of the RF automated test equipment (ATE) used to perform wafer-level and fully packaged RF functionality tests, (b) limited test point access for the application and capture of test signals, (c) the long test development and application times, and (d) the lack of diagnostic tools to evaluate and improve the performance of loadboards and test resources in high-volume tests. In this thesis, a framework for the efficient production testing of high-performance RF modules and systems using low-cost ATE is presented. This framework uses low-speed, low-resolution test resources to generate reliable tests for complex RF systems. Also, the test resources will be evaluated and improved ahead of high-volume tests to improve test yield and throughput. The components of the proposed framework are: (1) Genetic ATPG for reliable test stimulus generation using low-resolution test resources: A genetic algorithm (GA) based automatic test pattern generator (ATPG) to optimize the alternate test stimulus for reliable testing of complex RF systems using low-resolution, low-cost test resources. These test resources may be on-chip or off-chip. (2) Concurrent voltage/current alternate test methodology: A testing framework for efficiently testing the high-frequency specifications of RF systems using low-frequency spectral and/or transient current signatures. Suitable on-chip and/or off-chip design-for-test (DfT) resources are used to enable the source and capture operations at lower frequencies. (3) Loadboard checker: A checker tool to accurately characterize/diagnose the DfT resources on the RF loadboards used to enable test of RF devices/systems using low-cost ATE. (4) Advanced test signal processing algorithms: The performance of the low-cost ATE resources, in terms of their linearity/resolution, will be evaluated and improved to enable the accurate capture of the test response signals.