Th.--Sci. phys.--Grenoble--I.N.P.G., 1979. N°: DE 73.

Submitted by Nathália Faria da Silva (nathaliafsilva.ufv@gmail.com) on 2017-07-18T15:00:35Z No. of bitstreams: 1 texto completo.pdf: 160640 bytes, checksum: 08a7f32561ec04d17fae1c6fc129e073 (MD5) / Made available in DSpace on 2017-07-18T15:00:35Z (GMT). No. of bitstreams: 1 texto completo.pdf: 160640 bytes, checksum: 08a7f32561ec04d17fae1c6fc129e073 (MD5) Previous issue date: 2005-11-24 / Um experimento foi realizado com 2.112 pintos de corte machos da linhagem Ross com o objetivo de avaliar a influência da utilização de aditivos não-nutrientes (antibiótico, prebiótico e simbiótico) sobre o desempenho e as características de carcaça de frangos de corte. As aves foram distribuídas em delineamento em blocos casualizados, em arranjo fatorial 2 x 6 (milho x aditivo), totalizando 12 tratamentos, com oito repetições e 22 aves por unidade experimental. As rações foram formuladas à base de milho e farelo de soja, utilizando-se, na metade dos tratamentos, milho de qualidade normal (T 1 , T 2 , T 3 , T 4 , T 5 e T 6 ) e, na outra metade, milho de baixa qualidade (T 7 , T 8 , T 9 , T 10 , T 11 e T 12 ). Os tratamentos consistiram de T 1 e T 7 = ração basal (RB); T 2 e T8 = RB + antibiótico; T 3 e T 9 , RB + Simbiótico; T 4 e T 10 = RB + MOS 1 (0,5kg/t); T 5 e T 11 = RB + MOS 1 (1,0kg/t); e T 6 e T 12 = RB + MOS 2 (1,0kg/t). Para aumentar o desafio sanitário, além da cama reutilizada, foi fornecida uma solução contendo água misturada com cama, por um período de 8 horas, no 9 o , 16o e 24o dias de idade. Aos 21 e aos 42 dias de idade, foram avaliados o ganho de peso, o consumo de ração e a conversão alimentar e, aos 42 dias, as características de carcaça, o fator de produção e o peso relativo do fígado. Verificou-se efeito do aditivo somente para ganho de peso aos 21 dias e para ganho de peso e consumo de ração aos 42 dias, não se observando efeito dos aditivos sobre as demais características avaliadas. Os prebióticos à base de manonoligossacarídeos e o simbiótico podem substituir o antibiótico avilamicina nas rações para aves, pois não promoveram perdas no desempenho das aves, independentemente da qualidade do milho. O uso de milho de baixa qualidade piorou o desempenho zootécnico, provocando perdas no rendimento e na qualidade de carcaça de frangos de corte. / The experiment was conducted with 2112 broilers chicks, ROSS, with the objective to evaluate the use of non-nutrient additives (antibiotic, prebiotic and symbiotic) on performance and carcass parameters of broiler chickens. The experimental period was from 1 to 21 and 22 to 42 d. The birds were distributed in a complete randomized block design in factorial scheme 2 x 6 (corn x additive), totalizing 12 treatments with eight repetitions and 22 birds per experimental unit. Diets were based on corn and soybean meal, however half the treatments utilized standard quality corn (T 1 , T 2 , T 3 , T 4 , T 5 e T 6 ) and the other half low quality corn (T 7 , T 8 , T 9 , T 10 , T 11 e T 12 ). The treatments were: T 1 and T 7 , basal diet (BD); T 2 and T8, BD + antibiotic; T 3 and T 9 , BD + Symbiotic; T 4 and T 10 , BD + MOS1 (0,5kg/t); T 5 and T 11 , BD + MOS 1 (1,0kg/t) and T 6 and T 12 BD + MOS 2 (1,0kg/t). To increase sanitary challenge, besides of using reutilized bedding, a water solution with broiler bedding was used for eight hour on days 9o, 16o and 24o of the experimental period. At 21 and 42 days of age, weight gain, feed intake and feed conversion were evaluate, and also at the 42 days of age, carcass evaluation, production index and relative liver weight. It was observed additive effect on weight gain at 21d, and on weight gain and feed intake at 42 d. For the other parameters studied, there was no significant effect. It was concluded that prebiotic based on mannaoligosaccharides and symbiotic can substitute the antibiotic (avilamicin) in broiler diets, without affecting performance, independent from the corn quality. The use of low quality corn resulted in worse performance and decreased carcass yield and quality.

OLIVEIRA, Erlania Lima de. Propriedades Eletrônicas de Dispositivos MOS Baseados em SiC. 2005. 95 f. Dissertação (Mestrado em Física) - Programa de Pós-Graduação em Física, Departamento de Física, Centro de Ciências, Universidade Federal do Ceará, Fortaleza, 2005. / Submitted by Edvander Pires (edvanderpires@gmail.com) on 2015-05-07T17:23:34Z No. of bitstreams: 1 2005_dis_eloliveira.pdf: 1943111 bytes, checksum: 4c7f59af1ab6ffe6fa88b03b1c341459 (MD5) / Approved for entry into archive by Edvander Pires(edvanderpires@gmail.com) on 2015-05-07T17:24:15Z (GMT) No. of bitstreams: 1 2005_dis_eloliveira.pdf: 1943111 bytes, checksum: 4c7f59af1ab6ffe6fa88b03b1c341459 (MD5) / Made available in DSpace on 2015-05-07T17:24:15Z (GMT). No. of bitstreams: 1 2005_dis_eloliveira.pdf: 1943111 bytes, checksum: 4c7f59af1ab6ffe6fa88b03b1c341459 (MD5) Previous issue date: 2005 / O carbeto de silício (SiC) é considerado um material promissor para aplicações que demandam altas potências, altas freqüências, e para funcionamento em temperaturas elevadas e ambientes quimicamente hostis, condições nas quais as atuais tecnologias baseadas em Si e GaAs não oferecem performances satisfatórias. Esta versatilidade deve-se a características notáveis como grande gap de energia, alta mobilidade eletrônica, alta condutividade térmica, altos campos de ruptura dielétrica, estabilidade e resistência mecânica. Além disso, o SiC pode ser crescido em mais de 200 politipos envolvendo três estruturas cristalinas: cúbica (zincoblenda), hexagonal (wurtizita) e romboédrica. A vantagem mais significativa do SiC sobre outros semicondutores de gap largo é a capacidade de se crescer SiO2 termicamente, similar a do Si. Infelizmente, dispositivos baseados em SiC não podem competir com tecnologias baseadas em Si nas áreas de baixo custo, densidade funcional e temperaturas moderadas. Embora a tecnologia do SiC esteja evoluindo rapidamente, há ainda vários problemas a serem resolvidos como crescimento cristalino em larga escala, minimização de defeitos e otimização da performance dos dispositivos. A finalidade deste trabalho é desenvolver ferramentas teóricas e computacionais para a investigação das propriedades elétricas e eletrônicas de capacitores MOS baseados em SiC. O modelo físico utilizado baseia-se na solução das equações acopladas de Poisson e Schrödinger. Embora o modelo descrito seja geral o suficiente para ser aplicado em dispositivos mais complexos e geometrias tridimensionais, optou-se por um modelamento unidimensional, uma vez que os fenômenos físicos que regem o funcionamento básico de dispositivos MOSFET's podem ser perfeitamente capturados pelo modelamento unidimensional de capacitores MOS.

Submitted by Haroudo Xavier Filho (haroudo.xavierfo@ufpe.br) on 2016-02-26T16:11:44Z No. of bitstreams: 2 license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) 5.-Tesis doutorado Yesmin 2015 UFPE Bibliot.pdf: 2813580 bytes, checksum: c994d000e414c2f79bd7b8711d5f2714 (MD5) / Made available in DSpace on 2016-02-26T16:11:44Z (GMT). No. of bitstreams: 2 license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) 5.-Tesis doutorado Yesmin 2015 UFPE Bibliot.pdf: 2813580 bytes, checksum: c994d000e414c2f79bd7b8711d5f2714 (MD5) Previous issue date: 2015-06-05 / CAPES / CNPq / FACEPE / Neste trabalho, apresentamos a síntese e caracterização do material mesoporoso MCM-41 para o desenvolvimento de capacitores MOS. A motivação deste trabalho deve-se às propriedades interessantes que MCM-41 apresenta, tais como: área superficial e volume de poro grande e estrutura ordenada de poros. Inicialmente apresentamos a síntese do material mesoporoso MCM-41 pelo método Sol-Gel, e sua caracterização estrutural (DRX e IV), morfológica (MEV e TEM) e texturais (Análise de Adsorção e Dessorção de Nitrogênio), e fazemos uma comparação de resultados com o mesmo material produzido pela Sigma-Aldrich. Também foram obtidos filmes pelo método químico, que foram caracterizados por MEV e DRX e em seguida foram fabricados capacitores MOS. As medidas elétricas do capacitor MOS com dielétrico de MCM-41 foram comparadas com capacitores com dielétrico de SiO2 térmico. Os resultados mostraram uma clara diferença nas curvas de Corrente-Tensão. Conclui-se que a água confinada dentro do filme dielétrico é associada com os valores elevada de capacitância por unidade de área, estes valores permanecem altos depois do aquecimento, indicando que a resposta dielétrica é devida á água ligada ao material dielétrico, formando camadas paralelas á superfície do substrato. Capacitores de MCM-41 foram expostos a vários solventes polares e apolares, assim como á radiação gama e apresentaram distorção na resposta da capacitância e deslocamento nas curvas de corrente – tensão. Finalmente, capacitores de MCM-41 foram hidrolisados com o objetivo de aumentar a concentração dos grupos silanol na superfície do MCM-41 e como consequência alterar a capacitância do dispositivo. / In this work, we report the synthesis and characterization of MCM-41 mesoporous material for the development of devices types MOS capacitors. The motivation of this work is due to the MCM-41 interesting properties such as: surface area and pore volume large and pore ordered structure. Initially, we present a synthesis of MCM-41 mesoporous material by sol-gel method and their structural characterization (XRD and IR), morphological (SEM and TEM) and texture (Nitrogen Desorption and Adsorption Analysis) and make a comparison with the same material produced by Sigma. Also, films were obtained by chemical method, which were characterized by SEM and XRD, and then MOS capacitors were fabricated. The electrical characteristics MCM-4 MOS capacitors were compared with thermal SiO2, the results showing a clear difference in the voltage-current curves. It concludes that water confined within the dielectric film is associated with high values of capacitance per unit area these values remain high even after heating, indicating a dielectric response due to water strongly bonded to the dielectric material forming layers parallel to the substrate surface. The MCM-41 capacitors were exposed to various polar and nonpolar solvents and gamma radiation and showed good results were due to variations in the response to capacitance and the voltage-current curves showed displacement and distortion. Finally, the MCM-41 capacitors were hydrolyzed in order to be able to increase the concentration of silanol groups on the surface of MCM-41; as a consequence the material is more sensitive to moisture and therefore, the capacitance of the device response.

The significant growth in multimedia services and traffic (e.g. VoIP, video streaming and video gaming) in current and emerging mobile networks including the latest 4G Long-Term Evolution (LTE) networks and the rising user expectation for high Quality of Experience (QoE) for these services have posed real challenges to network operators and service providers. One of the key challenges is how to bring multimedia services to the end-user over resource-constrained mobile networks with a satisfactory QoE. Cost-effective solutions are needed for network operators to improve the bandwidth usage of these mobile networks. Therefore, scheduling schemes are of extreme importance in LTE, where scheduling algorithms are responsible for the overall efficiency of resource allocation in an LTE system. The aim of the project is to develop novel QoE-driven scheduling algorithms for improving system capacity in delivering multimedia services over downlink 3GPP LTE. This is to move away from traditional QoS-driven scheduling schemes to a QoE-driven scheme which guarantee end-user satisfaction in resource allocation. The main contributions of the thesis are threefold: 1. Performance of several existing scheduling algorithms for VoIP applications was evaluated thoroughly in terms of QoE metric (i.e. MOS), instead of QoS metrics (e.g. packet loss and delay). Using QoE metrics instead of QoS ones will facilitate the development of QoE-driven scheduling schemes in order to achieve optimised end-user experiences or optimised mobile system capacity. 2. A novel QoE-driven LTE downlink scheduling scheme for VoIP application was developed to maximize the number of users per cell at an acceptable MOS score. The proposed scheme achieved significant improvement in cell capacity at an acceptable quality (75% compared to MLWDF, and 250% compared to PF and EXP-PF in all three lower speed scenarios considered). 3. A QoE-driven LTE downlink scheduling scheme for multiservice multimedia applications was developed to improve the cell capacity with satisfactory QoE for both VoIP and video streaming services. The proposed algorithm performed well in a pedestrian scenario increasing cell capacity to double for video stream with ‘Rapid Movement’ (RM) content. For ‘Medium Movement’ (MM) video content, the capacity was increased about 20% compared to MLWDF and by 40% compared to EXP-PF. In a vehicular scenario, the proposed scheme managed to enhance the cell capacity for MM video stream case. The project has led to three publications (IEEE Globecom’12 – QoEMC Workshop, IEEE CCNC’15 and IEEE MMTC E-letter/May-2015). A journal paper is in preparation.

The main aim of the studies was to evaluate the modes of actions of Bio-Mos and the effect that it has on intestinal health as well as performance in broiler chickens. For the purpose of this study there were 2 main objectives. The first was to determine the effect of Bio-Mos as well as soluble mannan on salmonella colonization and to do this it was necessary to develop an in vivo pathogen challenge model, specifically designed for salmonella, using the chicken as animal model. The aim with this salmonella assay was to design a model that could accurately determine the efficacy of different components of the yeast cell wall at reducing or eliminating salmonella colonisation in chickens. The second objective was to evaluate the effect of Bio-Mos with or without the addition of a soluble mannan, fed at different inclusion levels, on chicken health. Specific parameters measured included feed conversion ratios (FCR), volatile fatty acid (VFA) analysis, antibiotic resistance amongst coliform populations, immunoglobulin quantification and gut morphology. Gut morphology measurements included villi height and width, crypt depth, muscularis thickness, goblet cell size and goblet cell density. The salmonella assay trial was not able to yield positive results for either the cell wall preparations or the positive control, indicating that there are some external factors that have to be addressed before this assay can be used to draw any accurate conclusions from. The second section of this study did show FCR differences between some of the treatments, but did not show numerically large differences for VFA production or antibiotic resistance, however the histological evaluation did yield interesting results. Measurements based on the villi height and width, crypt depth and muscularis thickness showed no significant differences between treatments but there was a treatment effect on the goblet cells. The goblet cells of chickens receiving cell wall preparations were statistically significantly larger and present at a higher density than those of the control treatment birds. In an attempt to develop the salmonella assay several aspects of the existing assay model were altered or eliminated. It is possible that the assay can work with some more adjustments, but due to time constrictions it was not possible to further explore alternative approaches. Little research has been done on the effect of nutrition on the goblet cells in chicken intestines. The results noted in this report warrant a more in-depth investigation into the exact modes of action resulting in the differences in goblet cells observed. The use of cell wall preparations on a commercial level holds many advantages, as cell wall preparations appear to affect animal health in a positive way. / Dissertation (MSc (Agric) : Animal Nutrition)--University of Pretoria, 2008. / Animal and Wildlife Sciences / MSc (Agric) / unrestricted

Les systèmes de gestion de l'énergie exigent des convertisseurs de puissance pour fournir une conversion de puissance adaptée à diverses utilisations. Il existe différents types de convertisseurs de puissance, tel que les amplificateurs de puissance de classe D, les demi-ponts, les ponts complets, les amplificateurs de puissance de classe E, les convertisseurs buck et dernièrement les convertisseurs boost. Prenons par exemple les dispositifs implantables, lorsque l'énergie est prélevée de la source principale, des convertisseurs de puissance buck ou boost sont nécessaires pour traiter l'énergie de l'entrée et fournir une énergie propre et adaptée aux différentes parties du système. D'autre part, dans les stations de charge des voitures électriques, les nouveaux téléphones portables, les stimulateurs neuronaux, etc., l'énergie sans fil a été utilisée pour assurer une alimentation à distance, et des amplificateurs de puissance de classe E sont développés pour accomplir cette tâche. Les amplificateurs de puissance de classe D sont un excellent choix pour les casques d'écoute ou les haut-parleurs en raison de leur grande efficacité. Dans le cas des interfaces de capteurs, les demi-ponts et les ponts complets sont les interfaces appropriées entre les systèmes à faible et à forte puissance. Dans les applications automobiles, l'interface du capteur reçoit le signal du côté puissance réduite et le transmet à un réseau du côté puissance élevée. En outre, l'interface du capteur doit recevoir un signal du côté haute puissance et le convertir vers la côté basse puissance. Tous les systèmes mentionnés ci-dessus nécessitent l'inclusion d'un pilote de porte spécifique dans les circuits, selon les applications. Les commandes de porte comprennent généralement un décalage du niveau de commande niveau supérieur, le levier de changement de niveau inférieur, une chaîne de tampon, un circuit de verrouillage sous tension, un circuit de temps mort, des portes logiques, un inverseur de Schmitt et un mécanisme de démarrage. Ces circuits sont nécessaires pour assurer le bon fonctionnement des systèmes de conversion de puissance. Un circuit d'attaque de porte reconfigurable prendrait en charge une vaste gamme de convertisseurs de puissance ayant une tension d'entrée V[indice IN] et un courant de sortie I[indice Load] variables. L'objectif de ce projet est d'étudier intensivement les causes de différentes pertes dans les convertisseurs de puissance et de proposer ensuite de nouveaux circuits et méthodologies dans les différents circuits des conducteurs de porte pour atteindre une conversion de puissance avec une haute efficacité et densité de puissance. Nous proposons dans cette thèse de nouveaux circuits de gestion des temps mort, un Shapeshifter de niveau plus élevé et un Shapeshifter de niveau inférieur avec de nouvelles topologies qui ont été pleinement caractérisées expérimentalement. De plus, l'équation mathématique du temps mort optimal pour les faces haute et basse d'un convertisseur buck est dérivée et expérimentalement prouvée. Les circuits intégrés personnalisés et les méthodologies proposées sont validés avec différents convertisseurs de puissance, tels que les convertisseurs semi-pont et en boucle ouverte, en utilisant des composants standard pour démontrer leur supériorité sur les solutions traditionnelles. Les principales contributions de cette recherche ont été présentées à sept conférences prestigieuses, trois articles évalués par des pairs, qui ont été publiés ou présentés, et une divulgation d'invention. Une contribution importante de ce travail recherche est la proposition d'un nouveau générateur actif CMOS intégré dédié de signaux sans chevauchement. Ce générateur a été fabriqué à l'aide de la technologie AMS de 0.35µm et consomme 16.8mW à partir d'une tension d'alimentation de 3.3V pour commander de manière appropriée les côtés bas et haut d'un demi-pont afin d'éliminer la propagation. La puce fabriquée est validée de façon expérimentale avec un demi-pont, qui a été mis en œuvre avec des composants disponibles sur le marché et qui contrôle une charge R-L. Les résultats des mesures montrent une réduction de 40% de la perte totale d'un demi-pont de 45V d'entrée à 1MHz par rapport au fonctionnement du demi-pont sans notre circuit intégré dédié. Le circuit principal du circuit d'attaque de grille côté haut est le décaleur de niveau, qui fournit un signal de grande amplitude pour le commutateur de puissance côté haut. Une nouvelle structure de décalage de niveau avec un délai de propagation minimal doit être présentée. Nous proposons une nouvelle topologie de décalage de niveau pour le côté haut des drivers de porte afin de produire des convertisseurs de puissance efficaces. Le SL présente des délais de propagation mesurés de 7.6ns. Les résultats mesurés montrent le fonctionnement du circuit présenté sur la plage de fréquence de 1MHz à 130MHz. Le circuit fabriqué consomme 31.5pW de puissance statique et 3.4pJ d'énergie par transition à 1kHz, V[indice DDL] = 0.8V , V[indice DDH] = 3.0V, et une charge capacitive C[indice L] = 0.1pF. La consommation énergétique totale mesurée par rapport à la charge capacitive de 0.1 à 100nF est indiquée. Un autre nouveau décalage vers le bas est proposé pour être utilisé sur le côté bas des pilotes de portes. Ce circuit est également nécessaire dans la partie Rₓ du réseau de bus de données pour recevoir le signal haute tension du réseau et délivrer un signal de faible amplitude à la partie basse tension. L'une des principales contributions de ces travaux est la proposition d'un modèle de référence pour l'abaissement de niveau à puissance unique reconfigurable. Le circuit proposé pilote avec succès une gamme de charges capacitives allant de 10fF à 350pF. Le circuit présenté consomme des puissances statiques et dynamiques de 62.37pW et 108.9µW, respectivement, à partir d'une alimentation de 3.3V lorsqu'il fonctionne à 1MHz et pilote une charge capacitive de 10pF. Les résultats de la simulation post-layout montrent que les délais de propagation de chute et de montée dans les trois configurations sont respectivement de l'ordre de 0.54 à 26.5ns et de 11.2 à 117.2ns. La puce occupe une surface de 80µm × 100µm. En effet, les temps morts des côtés hauts et bas varient en raison de la différence de fonctionnement des commutateurs de puissance côté haut et côté bas, qui sont respectivement en commutation dure et douce. Par conséquent, un générateur de temps mort reconfigurable asymétrique doit être ajouté aux pilotes de portes traditionnelles pour obtenir une conversion efficace. Notamment, le temps mort asymétrique optimal pour les côtés hauts et bas des convertisseurs de puissance à base de Gan doit être fourni par un circuit de commande de grille reconfigurable pour obtenir une conception efficace. Le temps mort optimal pour les convertisseurs de puissance dépend de la topologie. Une autre contribution importante de ce travail est la dérivation d'une équation précise du temps mort optimal pour un convertisseur buck. Le générateur de temps mort asymétrique reconfigurable fabriqué sur mesure est connecté à un convertisseur buck pour valider le fonctionnement du circuit proposé et l'équation dérivée. De plus le rendement d'un convertisseur buck typique avec T[indice DLH] minimum et T[indice DHL] optimal (basé sur l'équation dérivée) à I[indice Load] = 25mA est amélioré de 12% par rapport à un convertisseur avec un temps mort fixe de T[indice DLH] = T[indice DHL] = 12ns. / Power management systems require power converters to provide appropriate power conversion for various purposes. Class D power amplifiers, half and full bridges, class E power amplifiers, buck converters, and boost converters are different types of power converters. Power efficiency and density are two prominent specifications for designing a power converter. For example, in implantable devices, when power is harvested from the main source, buck or boost power converters are required to receive the power from the input and deliver clean power to different parts of the system. In charge stations of electric cars, new cell phones, neural stimulators, and so on, power is transmitted wirelessly, and Class E power amplifiers are developed to accomplish this task. In headphone or speaker driver applications, Class D power amplifiers are an excellent choice due to their great efficiency. In sensor interfaces, half and full bridges are the appropriate interfaces between the low- and high-power sides of systems. In automotive applications, the sensor interface receives the signal from the low-power side and transmits it to a network on the high-power side. In addition, the sensor interface must receive a signal from the high-power side and convert it down to the low-power side. All the above-summarized systems require a particular gate driver to be included in the circuits depending on the applications. The gate drivers generally consist of the level-up shifter, the level-down shifter, a buffer chain, an under-voltage lock-out circuit, a deadtime circuit, logic gates, the Schmitt trigger, and a bootstrap mechanism. These circuits are necessary to achieve the proper functionality of the power converter systems. A reconfigurable gate driver would support a wide range of power converters with variable input voltage V[subscript IN] and output current I[subscript Load]. The goal of this project is to intensively investigate the causes of different losses in power converters and then propose novel circuits and methodologies in the different circuits of gate drivers to achieve power conversion with high-power efficiency and density. We propose novel deadtime circuits, level-up shifter, and level-down shifter with new topologies that were fully characterized experimentally. Furthermore, the mathematical equation for optimum deadtimes for the high and low sides of a buck converter is derived and proven experimentally. The proposed custom integrated circuits and methodologies are validated with different power converters, such as half bridge and open loop buck converters, using off-the-shelf components to demonstrate their superiority over traditional solutions. The main contributions of this research have been presented in seven high prestigious conferences, three peer-reviewed articles, which have been published or submitted, and one invention disclosure. An important contribution of this research work is the proposal of a novel custom integrated CMOS active non-overlapping signal generator, which was fabricated using the 0.35−µm AMS technology and consumes 16.8mW from a 3.3−V supply voltage to appropriately drive the low and high sides of the half bridge to remove the shoot-through. The fabricated chip is validated experimentally with a half bridge, which was implemented with off-the-shelf components and driving a R-L load. Measurement results show a 40% reduction in the total loss of a 45 − V input 1 − MHz half bridge compared with the half bridge operation without our custom integrated circuit. The main circuit of high-side gate driver is the level-up shifter, which provides a signal with a large amplitude for the high-side power switch. A new level shifter structure with minimal propagation delay must be presented. We propose a novel level shifter topology for the high side of gate drivers to produce efficient power converters. The LS shows measured propagation delays of 7.6ns. The measured results demonstrate the operation of the presented circuit over the frequency range of 1MHz to 130MHz. The fabricated circuit consumes 31.5pW of static power and 3.4pJ of energy per transition at 1kHz, V[subscript DDL] = 0.8V , V[subscript DDH] = 3.0V , and capacitive load C[subscript L] = 0.1pF. The measured total power consumption versus the capacitive load from 0.1pF to 100nF is reported. Another new level-down shifter is proposed to be used on the low side of gate drivers. Another new level-down shifter is proposed to be used on the low side of gate drivers. This circuit is also required in the Rₓ part of the data bus network to receive the high-voltage signal from the network and deliver a signal with a low amplitude to the low-voltage part. An essential contribution of this work is the proposal of a single supply reconfigurable level-down shifter. The proposed circuit successfully drives a range of capacitive load from 10fF to 350pF. The presented circuit consumes static and dynamic powers of 62.37pW and 108.9µW, respectively, from a 3.3 − V supply when working at 1MHz and drives a 10pF capacitive load. The post-layout simulation results show that the fall and rise propagation delays in the three configurations are in the range of 0.54 − 26.5ns and 11.2 − 117.2ns, respectively. Its core occupies an area of 80µm × 100µm. Indeed, the deadtimes for the high and low sides vary due to the difference in the operation of the high- and low-side power switches, which are under hard and soft switching, respectively. Therefore, an asymmetric reconfigurable deadtime generator must be added to the traditional gate drivers to achieve efficient conversion. Notably, the optimal asymmetric deadtime for the high and low sides of GaN-based power converters must be provided by a reconfigurable gate driver to achieve efficient design. The optimum deadtime for power converters depends on the topology. Another important contribution of this work is the derivation of an accurate equation of optimum deadtime for a buck converter. The custom fabricated reconfigurable asymmetric deadtime generator is connected to a buck converter to validate the operation of the proposed circuit and the derived equation. The efficiency of a typical buck converter with minimum T[subscript DLH] and optimal T[subscript DHL] (based on the derived equation) at I[subscript Load] = 25mA is improved by 12% compared to a converter with a fixed deadtime of T[subscript DLH] = T[subscript DHL] = 12ns.

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No description available.

A study was carried out to investigate the effects of a drug-free feeding program on broiler performances. A total of 2,496 Cobb 500 chicks were randomly assigned to one of four dietary treatments with each group replicated 13 times. The four diets evaluated were: 1) negative control (NC): basal diet without growth promoter or coccidiostat; 2) positive control (PC): diet 1 + Lincomycin; 3) Program 1 (PG1): diet 1 + Bio-Mos®, Vegpro®, MTB-100®, Acid Pak 4-Way®, and All-Lac XCL®; 4) Program 2 (PG2): diet 1 + Bio-Mos® and All-Lac XCL®. Additives were used at commercially recommended rates. All chicks were vaccinated with a live oocyst coccidia vaccine on d 0 at the hatchery. Four phases of feeding were used during the trial with changes occurring at d 14, 28, and 35. Performance values measured were body weight, feed intake, yield, and mortality, while body weight gain and feed conversation rate (FCR) were calculated. Chicks were challenged with coccidia at d 14 to evaluate the protective effect of the feeding programs and coccidia vaccination. Segments of duodenum, ileum, and ceca were removed to measure intestinal morphology. Final body weight gains of birds on PC (2.736 kg) were greater (P < 0.05) compared to NC (2.650 kg), while birds on PG1 (2.681 kg) and PG2 (2.710 kg) were similar to positive and negative control. Overall, feed intake was similar across the treatments with the exception of period 2 (15 to 28 days) when birds consumed more (P < 0.05) of PC and PG1 compared to NC. Cumulative FCR at d 35 and 49 was improved (P < 0.05) in birds consuming PC and PG2 when compared to NC. Overall, birds consuming NC had greater mortality (P < 0.05; 12%) compared to PC (7.6 %), PG1 (4.6%) and PG2 (6.7 %) with most of the mortality occurring from d 0 to d 28. Mortality for birds consuming PG1 was also lower (P < 0.05) compared to the PC. There were no dietary effects on lesion scores or yields of processed products at d 42 (females) or d 49 (males). Interaction of dietary treatments with age and days of age alone showed effects (P < 0.0001) on the morphology of duodenum, ileum, and ceca. Lamina propria in ceca was thicker (P < 0.008) in birds consuming NC compared to PG1 and PG2. This study indicated that feeding birds without growth promoters resulted in greater mortality and decreased performance compared to using an antibiotic, while Bio-Mos® in combination with All-Lac XCL® helped to reduce the negative effects. / Master of Science