Thesis (M.S.)--Oregon State University, 1995. / Typescript (photocopy). Includes bibliographical references (leaves 34-35). Also available via the World Wide Web.

Throughput and latency are critical parameters in multiprocessor interconnection networks. These parameters are governed by the combination of routing node and interconnect performance. Recent years have seen several new interconnect technologies reach the stage of maturity where they may be applied in practical systems. One such technology is free-space optical interconnect. The problems of wiring density, low data-rates and limited integrated circuit (IC) pin-out are neatly side-stepped by the use of optical interconnect. In order to make practical use of optical interconnects, packet routing node data rates must increase by an order of magnitude or more. At the same time, latency cannot be sacrificed as it is critical to the performance of multi-processor systems. One possible avenue to meeting the required performance is to re-examine the hardware cost of packet router architectures and attempt to improve them. The research presented in this thesis attempts to do exactly that. The result of this research is a packet router architecture known as the Cellular Router. The router allows massive throughput, while maintaining low latency. The architecture is designed to minimise silicon area and maximise achievable clock rate in any given fabrication process. The router is scalable, in the sense that area requirements increase linearly along one axis in proportion to increased throughput. This thesis describes a novel packet router architecture. It is a compact, power efficient, scalable design that is capable of exceptionally high throughput. The Cellular Router allows the benefits of free-space optical interconnects to be effectively utilised in multi-processor systems.

No description available.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Computer Science, 2008. / Includes bibliographical references.

This paper presents an expandable multiprocessor system design based on: (a) an INTEL 80188 based microcomputer as the basic processing element; (b) a multi-channel, multi-access, processor independent interprocessor communications subnetwork with data transfer rates of 250 Kbps or 1 Mbps per channel. The basic system design consists of two IBM PC expansion cards--a single processor IBM PC Interface Card, and a Quad Processor Card containing four 80188 CPUs. Each processor has access to two separate interprocessor (IP) serial data channels. An IP channel supports as many as 16 processors using a token bus data link control. IP communications is either direct or routed via intervening processors to support an unlimited number of processors in a given system.

Graduate

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The multimedia capabilities of computers have recently become the focus of computer developers due to the increasing demand for advanced computer graphics and new media capabilities, such as video conferencing, 3-D visualization, and animation. To support these multimedia capabilities, specialized graphics hardware, such as MPEG encoding/decoding card, 3-D graphics card, video card, and sound card, are widely used today, but the price of a separate board is expensive. Therefore, the processor must be redesigned from the ground up to handle new media applications. Although these multimedia functions are typically consist of simple operations, their sheer volume of computation creates a flood of data. To support such large volumes of multimedia data computation, Sun Microsystems implemented a specialized instruction set, called VIS[Trademark] (Visual Instruction Set), which is Single Instruction Multiple Data (SIMD) style of instruction. The basic concept behind VIS is to break the pipeline of the Floating Point Unit (FPU) into two or four parallel pipelines to perform four or eight separate 16-bit or 8-bit integer additions in one cycle, instead of one floating-point addition. The Electronics and Telecommunications Research Institute (ETRI) in South Korea has researched a 64-bit multimedia enhanced on-chip multiprocessor named Raptor, which has quad processors and shares a common Graphics Control Unit (GCU). Raptor implements multimedia support directly on the processor using specialized instructions, GCU Instructions, which are variant of VIS instructions, and hardware supports. Each processor of Raptor executes multimedia applications independently and the independent streams or threads of multimedia instructions compute for and share a single GCU. The major theme of this thesis is to design the GCU architecture and to simulate it. The GCU can simultaneously execute the independent instruction streams from four General Processors (GP) and resolves the dependencies among the instructions dynamically. / Graduation date: 1998

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