Les principaux résultats de recherche présentés dans cette thèse de Doctorat concernent la proposition de nouvelles méthodologies de spécifications et de dimensionnement ainsi que des techniques de mise en œuvre de structures de filtrage et de conception d'architectures matérielles reconfigurables pour la sélection numérique des canaux radio dans un contexte de réception multistandard. Les résultats obtenus à l'issue de cette thèse constituent une contribution à un nouvel axe de recherche qui vise à développer de nouvelles technologies pour des équipements radio flexibles, multi-service, multi-standards, multi-bandes, re-configurables mais tout en limitant la complexité de traitement et d'implantation matérielle en vue de réduire d'avantage l'encombrement des équipements portables ainsi que leur consommation d'énergie. Notre première étape d'étude a concerné la définition de structure et de méthode de dimensionnement d'un récepteur radio à conversion directe doté de fonctionnalités large bande et multi-bande. Une méthode a aussi été établie pour déterminer les spécifications des étages de sélection des canaux en tenant compte de la structure de filtrage en cascade, des profils des signaux et interférents radio ainsi que des effets de repliement de spectre. Les résultats de synthèse sur FPGA ont permis de mettre en évidence les performances en terme de qualité de filtrage et d'optimisation des ressources d'implantation matérielle.

Ce mémoire fait tout d’abord l’état de l’art des filtres reconfigurables (passifs et actifs) pour les radiocommunications. Les différentes architectures de réception sont comparées pour déterminer celles qui sont les mieux adaptées aux récepteurs de type multistandard. Les concepts de radio logicielle et de radio cognitive ainsi que la façon de les mettre en œuvre sont ensuite indiqués afin de souligner l’intérêt d’utiliser des filtres reconfigurables. Les notions de filtres réglables, reconfigurables et agiles qui sont alors comparées illustrent tout l’intérêt des filtres agiles. Une nouvelle théorie qui permet pour la première fois la réalisation de filtres passe bande du second ordre entièrement actifs à fréquence agile est ensuite introduite. Un amplificateur de contre réaction dont le gain est réglable permet de modifier facilement la valeur de la fréquence centrale du filtre obtenu. Cette théorie est ensuite généralisée et ses nouvelles propriétés sont étudiées. Il en résulte alors une plage de réglage de la fréquence beaucoup plus étendue. Des filtres passe bande ont été réalisés en mode courant en technologie SiGe BiCMOS 0.25 µm de STMicroelectroincs à partir de convoyeurs de courant contrôlés (CCCII). Les résultats de simulation obtenus pour ces différents filtres confirment les avantages de cette théorie. Ils montrent ainsi que la généralisation précédente conduit à des structures entièrement actives dont la plage de réglage de la fréquence augmente et la puissance dissipée diminue. Des résultats de mesure obtenus sous pointes pour un filtre passe bande réalisé dans la technologie précédente sont donnés. Ils sont aussi en parfait accord avec cette théorie. Cette nouvelle approche permettra de réaliser des filtres agiles pour les récepteurs multistandard de radiocommunication. / In this thesis, we explore the state of the art of reconfigurable filters (passive and active) used in radio-communications. Different receiving architectures are compared to determine the most suitable for multi-standard devices. The concept of software and cognitive radio as well as the means to implement them are indicated in order to highlight the advantage of reconfigurable filters. The concepts of tunable, reconfigurable and agile filters are compared, illustrating the advantage agile ones. A new theory which allows, for the first time, the realization of second order band-pass fully active filters is then introduced. A feedback amplifier with tunable gain allows modifying easily the center frequency of the resulting filter; this theory is then generalized and its new properties are studied. This results in a large frequency tuning range. Current mode band-pass filters are implemented in SiGe BiCMOS 0.25 µm from STMicroelectroincs using current controlled conveyors (CCCII), the simulation results confirm the interest of this theory. They also show that the generalization leads to entirely active structures whose tuning range increases while its power dissipation decreases. The measurements carried out on the fabricated chip are given; they are in perfect agreement with this theory. The new approach allows realizing agile filters for multi-standard radio-communication receivers.

Ces dernières années, le développement durable, notamment le contrôle de la consommation de nos appareils électriques, est devenu un enjeu majeur de notre société. L'essor de la domotique associé à cette problématique implique la nécessité d'optimiser le bilan énergétique de chaque dispositif électrique. L'objectif de cette thèse est la réalisation d'un amplificateur faible bruit (LNA) qui propose deux modes de fonctionnement suivant la qualité du signal reçu: un mode haute performance et un mode basse consommation.Afin de satisfaire la problématique liée aux systèmes multistandard, l'architecture sélectionnée pour l'amplificateur faible bruit est la topologie distribuée. En effet, elle est connue pour ses performances en terme de bande passante et permet un gain en puissance accordable. Une méthode de conception est proposée, basée sur la technologie GaAs de la fonderie TriQuint Semiconducteur Texas. Les mesures réalisées sur le LNA dans sa configuration haute performance se situe au niveau de l'état de l'art. Pour le mode basse consommation, on obtient de bonnes performances tout en réduisant sa consommation de 91%.Enfin, une stratégie de reconfiguration innovante est proposée basée sur l'intégration de notre LNA dans un récepteur homodyne. Elle permet de réduire de manière significative la consommation du récepteur, dans le cas où la puissance reçue permet un fonctionnement en mode basse consommation (contraintes sur le Bit Error Rate (BER) vérifiées). En considérant chaque puissance reçue de manière équiprobable, notre récepteur reconfigurable a une consommation réduite de 77% par rapport à un récepteur classique qui possède un seul mode de fonctionnement (mode haute performance). / In recent years, the sustainable development, especially the control of the electrical appliances' consumption, has became a major issue in our society. The optimisation of each electrical devices' energy is needed to reduce the consumption of home appliances. The objective of this thesis is the realization of a low noise amplifier (LNA) that offers two modes of operation depending on the quality of the received signal: a high performance mode and a low consumption mode.In order to meet the problem related to multistandard systems, the distributed architecture is selected for low noise amplifier. Indeed, it is known for its wide bandwidth and tunable power gain. A design method is proposed, which is based on GaAs technology of TriQuint Semiconductor Texas foundry. The LNA's high performance mode measurement results is at the level of the state of the art. For the low consumption mode, LNA shows good performance while reducing power consumption by 91%.Finally, an innovative reconfiguration strategy is defined. It's applied to a homodyne receiver based on the integration of our LNA. It reduces significantely the receiver's consumption in case where the received power allows the receiver operates in low power mode (constraint of the Bit Error Rate (BER) is verified). Considering each received power is equiprobable, our reconfigurable receiver saves consumption by 77% compared to a conventional receiver that has a single mode (high performance mode).

Nesta dissertação é apresentado o projeto de um sintetizador de frequência atingindo as especificações dos padrões de comunicação sem-fio GSM e Bluetooth. O sintetizador é baseado em um PLL (Phase Locked Loop) de arquitetura N-fracionário com modulador . No primeiro estágio do projeto do sintetizador é proposto um algoritmo para o plano de frequências, o qual considera a caraterística multipadrão do sintetizador. O projeto dos blocos que compõem o PLL (VCO, divisores de frequência, modulador , PFD e bomba de carga) é apresentado junto com o layout e algumas simulações. A programação geométrica é aplicada ao projeto do VCO. Finalmente, é proposta uma estratégia para o projeto do filtro atingindo as especificações do sintetizador de frequência. O circuito projetado foi fabricado no processo CMOS 0,35µm da AMS (Austria Micro Systems). Todos os componentes do PLL foram integrados no chip incluindo o VCO e o filtro, e a área total foi de 0,9mm2 incluindo os pads. O circuito projetado tem um baixo consumo de potência de 14mW usando uma tens~ao de alimentação de 3V. O ruído de fase medido foi -114dBc/Hz@400kHz no caso de GSM (FOUT =902,6MHz) e -121dBc/Hz@3MHz no caso de Bluetooth (FOUT =2,44GHz). A resposta transiente do PLL quando muda desde o primeiro até o último canal para cada padrão foi testada, o lock time medido em GSM foi de 208µs e 157µs em Bluetooth. O objetivo principal do funcionamento multipadrão, que é o uso compartilhado da maioria dos blocos por todos os padrões, foi atingido. As caraterísticas de desempenho medidas mostram excelente concordância com os valores simulados, indicando o êxito das estratégias usadas no projeto, simulação e teste do sintetizador de frequência. Os resultados foram comparados com outros trabalhos publicados mostrando que o sintetizador projetado neste trabalho tem menor consumo de potência e pequena ocupação de área. / This work presents the design of a frequency synthesizer achieving the specifications of the GSM and Bluetooth standards. The frequency synthesizer is based on a PLL (Phase Locked Loop) of N-fractional architecture using a modulator. In the first step of the frequency synthesizer design an algorithm for the frequency plan, considering the multistandard characteristic of the synthesizer, was proposed. The design of the building blocks of the PLL (VCO, frequency dividers, modulator, PFD and charge pump) is presented together with the layout and some simulation results. Geometric programming was applied to the VCO design. Finally, an strategy for the filter design achieving the frequency synthesizer specifications was proposed. The designed synthesizer was fabricated in the 0.35µm CMOS process of AMS (Austria Micro Systems). All the PLL components were integrated on-chip including the VCO and the filter, the occupied area was 0.9mm2 with the pads. The designed circuit has a low power consumption of 14mW using a 3V voltage supply. The phase noise measured for GSM (FOUT =902.6MHz) was -114dBc/Hz@400kHz and for Bluetooth (FOUT =2.44GHz) was -121dBc/Hz@3MHz. The transient response of the PLL when switching from the first to the last channel for each standard was tested, the lock time measured in GSM was 208µs and 157µs in Bluetooth. The main objective of the multistandard operation sharing most of the blocks between all the standards was achieved. The measured performance characteristics show excelent agreement with the simulated values, implying that the strategies used in the design, simulation and testing of the frequency synthesizer were succesfull. The results were compared with other published works showing that the synthesizer designed in this work has a lower power consumption and smaller area.

Nesta dissertação é apresentado o projeto de um sintetizador de frequência atingindo as especificações dos padrões de comunicação sem-fio GSM e Bluetooth. O sintetizador é baseado em um PLL (Phase Locked Loop) de arquitetura N-fracionário com modulador . No primeiro estágio do projeto do sintetizador é proposto um algoritmo para o plano de frequências, o qual considera a caraterística multipadrão do sintetizador. O projeto dos blocos que compõem o PLL (VCO, divisores de frequência, modulador , PFD e bomba de carga) é apresentado junto com o layout e algumas simulações. A programação geométrica é aplicada ao projeto do VCO. Finalmente, é proposta uma estratégia para o projeto do filtro atingindo as especificações do sintetizador de frequência. O circuito projetado foi fabricado no processo CMOS 0,35µm da AMS (Austria Micro Systems). Todos os componentes do PLL foram integrados no chip incluindo o VCO e o filtro, e a área total foi de 0,9mm2 incluindo os pads. O circuito projetado tem um baixo consumo de potência de 14mW usando uma tens~ao de alimentação de 3V. O ruído de fase medido foi -114dBc/Hz@400kHz no caso de GSM (FOUT =902,6MHz) e -121dBc/Hz@3MHz no caso de Bluetooth (FOUT =2,44GHz). A resposta transiente do PLL quando muda desde o primeiro até o último canal para cada padrão foi testada, o lock time medido em GSM foi de 208µs e 157µs em Bluetooth. O objetivo principal do funcionamento multipadrão, que é o uso compartilhado da maioria dos blocos por todos os padrões, foi atingido. As caraterísticas de desempenho medidas mostram excelente concordância com os valores simulados, indicando o êxito das estratégias usadas no projeto, simulação e teste do sintetizador de frequência. Os resultados foram comparados com outros trabalhos publicados mostrando que o sintetizador projetado neste trabalho tem menor consumo de potência e pequena ocupação de área. / This work presents the design of a frequency synthesizer achieving the specifications of the GSM and Bluetooth standards. The frequency synthesizer is based on a PLL (Phase Locked Loop) of N-fractional architecture using a modulator. In the first step of the frequency synthesizer design an algorithm for the frequency plan, considering the multistandard characteristic of the synthesizer, was proposed. The design of the building blocks of the PLL (VCO, frequency dividers, modulator, PFD and charge pump) is presented together with the layout and some simulation results. Geometric programming was applied to the VCO design. Finally, an strategy for the filter design achieving the frequency synthesizer specifications was proposed. The designed synthesizer was fabricated in the 0.35µm CMOS process of AMS (Austria Micro Systems). All the PLL components were integrated on-chip including the VCO and the filter, the occupied area was 0.9mm2 with the pads. The designed circuit has a low power consumption of 14mW using a 3V voltage supply. The phase noise measured for GSM (FOUT =902.6MHz) was -114dBc/Hz@400kHz and for Bluetooth (FOUT =2.44GHz) was -121dBc/Hz@3MHz. The transient response of the PLL when switching from the first to the last channel for each standard was tested, the lock time measured in GSM was 208µs and 157µs in Bluetooth. The main objective of the multistandard operation sharing most of the blocks between all the standards was achieved. The measured performance characteristics show excelent agreement with the simulated values, implying that the strategies used in the design, simulation and testing of the frequency synthesizer were succesfull. The results were compared with other published works showing that the synthesizer designed in this work has a lower power consumption and smaller area.

Cette thèse de Doctorat s'inscrit dans le domaine de la conception de circuits innovants pour la numérisation des signaux radio multistandard. La nouveauté dans ce travail de recherche provient de l'exploration, pour la première fois dans le domaine des systèmes radio, de l'apport de l'utilisation des techniques d'échantillonnage non uniforme (NUS, Non Uniform Sampling). L'innovation de recherche apportée concerne l'établissement de formulations analytiques pour le calcul des métriques d'évaluation des performances de la technique NUS et pour le dimensionnement d'un nouveau récepteur radio multistandard avec un convertisseur analogique numérique (ADC, Analog-to-Digital Converter) contrôlé par une horloge non uniforme. Les résultats de cette étude ont conduit à la synthèse d'un filtre anti-repliement unique pour les standards GSM/UMTS/WiFi et à la diminution la fréquence moyenne d'échantillonnage de l'ADC ce qui a permis de diminuer la consommation de puissance de l'ADC et d'éliminer le circuit du contrôle automatique de gain (AGC). L'étude analytique et la conception niveau système ont été complétées par la proposition d'une architecture numérique originale de génération d'horloge non uniforme permettant de s'affranchir des contraintes et limitations des oscillateurs non uniformes proposés dans la littérature. Ce circuit Pseudorandom Signal Sampler (PSS) a fait l'objet d'une synthèse et d'une validation préliminaire sur FPGA puis la conception d'un circuit VLSI en technologie CMOS numérique 65 nm. Les résultats d'implémentation du PSS ont permis d'obtenir, pour un facteur de quantification temporelle égal à 16, une surface active de 470 (µm)², des fréquences moyennes d'échantillonnage pouvant atteindre 200 MHz basées sur un synthétiseur de fréquence qui offre des fréquences jusqu'à 3.2 GHz et enfin une consommation de puissance de 1.45 à 290.4 µW pour des fréquences d'échantillonnage moyennes allant de 1 MHz à 200 MHz. Une validation expérimentale de l'étage de numérisation proposé a été effectuée grâce à la réalisation d'une plate-forme de test composée du circuit générateur PSS dont la sortie contrôle un ADC auquel est appliqué en entrée un signal sinusoïdal de test et d'un PC pour l'acquisition par FIFO mais aussi pour le traitement des données. Les résultats des tests expérimentaux obtenus ont permis de confirmer les résultats théoriques en termes de diminution de la consommation de l'ADC.

The wireless market is developing very fast today with a steadily increasing number of users all around the world. An increasing number of users and the constant need for higher and higher data rates have led to an increasing number of emerging wireless communication standards. As a result there is a huge demand for flexible and low-cost radio architectures for portable applications. Moving towards multistandard radio, a high level of integration becomes a necessity and can only be accomplished by new improved radio architectures and full utilization of technology scaling. Modern nanometer CMOS technologies have the required performance for making high-performance RF circuits together with advanced digital signal processing. This is necessary for the development of low-cost highly integrated multistandard radios. The ultimate solution for the future is a software-defined radio, where a single hardware is used that can be reconfigured by software to handle any standard. Direct analog-to-digital conversion could be used for that purpose, but is not yet feasible due to the extremely tough requirements that put on the analog-to-digital converter (ADC). Meanwhile, the goal is to create radios that are as flexible as possible with today’s technology. The key to success is to have an RF front-end architecture that is flexible enough without putting too tough requirements on the ADC. One of the key components in such a radio front-end is a multiband multistandard low-noise amplifier (LNA). The LNA must be capable of handling several carrier frequencies within a large bandwidth. Therefore it is not possible to optimize the circuit performance for just one frequency band as can be done for a single application LNA. Two different circuit topologies that are suitable for multiband multistandard LNAs have been investigated, implemented, and measured. Those two LNA topologies are: (i) wideband LNAs that cover all the frequency bands of interest (ii) tunable narrowband LNAs that are tunable over a wide range of frequency bands. Before analog-to-digital conversion the RF signal has to be downconverted to a frequency manageable by the analog-to-digital converter. Recently the concept of direct sampling of the RF signal and discrete-time signal processing before analog-to-digital conversion has drawn a lot of attention. Today’s CMOS technologies demonstrate very high speeds, making the RF-sampling technique appealing in a context of multistandard operation at GHz frequencies. In this thesis the concept of RF sampling and decimation is used to implement a flexible RF front-end, where the RF signal is sampled and downconverted to baseband frequency. A discrete-time switched-capacitor filter is used for filtering and decimation in order to decrease the sample rate from a value close to the carrier frequency to a value suitable for analog-to-digital conversion. To demonstrate the feasibility of this approach an RF-sampling front-end primarily intended for WLAN has been implemented in a 0.13 μm CMOS process.

Ces travaux de recherche s’inscrivent dans le cadre de la conception de récepteurs multistandard optimisés pouvant traiter des signaux à spécifications hétérogènes. L’idée est d’appliquer l’échantillonnage aléatoire au niveau de l’étage en bande de base d’un récepteur radio logicielle restreinte afin de tirer profit de son pouvoir d’anti-repliement. La nouveauté dans ces travaux est l’étude analytique de la réduction du repliement spectral par l’échantillonnage aléatoire à temps quantifié, candidat favorable à l’implémentation matérielle. Une deuxième contribution concerne aussi l’étude analytique de l’échantillonnage pseudo-aléatoire à temps quantifié (TQ-PRS) dont l’importance réside en sa grande facilité d’implémentation matérielle. Les formulations théoriques ont permis d’estimer l’atténuation des répliques en fonction du facteur de la quantification temporelle et du facteur du sur-échantillonnage. Les mesures de l’atténuation du repliement spectral ont permis de dimensionner l’étage en bande de base d’une architecture de réception multistandard. Le dimensionnement s’intéresse à différentes configurations de l’étage en bande de base régies par les performances du convertisseur analogique numérique (ADC) utilisé.Les travaux de recherche ont démontré que l’application du TQ-PRS au niveau de l’ADC mène soit à une réduction de l’ordre du filtre anti-repliement soit à une réduction de la fréquence d’échantillonnage. Un bilan global de la consommation de puissance a permis un gain de 30% de la consommation de l’étage en bande de base analogique. En tenant compte du générateur de l’horloge TQ-PRS et de l’étage de sélection numérique du canal, ce gain devient 25%. / The work presented in this Ph.D. dissertation deals with the design of multistandard radio receivers that process signals with heterogeneous specifications. The originality of these research activities comes from the application of random sampling at the baseband stage of a software defined radio receiver. The purpose behind the choice of random sampling is to take advantage of its alias-free feature. The originality of this work is the analytic proof of the alias attenuation feature of the time quantized random sampling, the implementation version of the random sampling. A second contribution concerns also the analytic study of the simplest implementation version of the random sampling, the time quantized pseudo-random sampling (TQ-PRS). Theoretical formulas allow the estimation of the alias attenuation in terms of time quantization factor and oversampling ratio. Alias attenuation measurement permits to design the baseband stage of the proposed multistandard radio receiver architecture. The design concerns different configuration of the baseband stage according to the performances of the used analog-to-digital converters (ADC). The TQPRS allows decreasing the anti-aliasing filter order or the sampling frequency. The design of the baseband stage reveals a difference on the choice of the time quantization factor for each standard. The power consumption budget analysis demonstrates a power consumption gain of 30% regarding the power consumption of the analog baseband stage. This gain becomes 27.5% when the TQ-PRS clock and the digital canal selection stages are considered.

The global market of mobile and wireless communications is witnessing explosive growth in size as well as radical changes. Third generation (3G) wireless systems have recently been deployed and some are still in the process. 3G wireless systems promise integration of voice and data communications with higher data rates and a superior quality of service compared to second generation systems. Unfortunately, more and more communication standards continue to be developed which ultimately requires specific RF/MW and baseband communication integrated circuits that are designed for functionality and compatibility with a specific type of network. Although communication devices such as cellular phones integrate different services such as voice, Bluetooth, GPS, and WLAN, each service requires its own dedicated radio transceiver which results in high power consumption and larger PCB area usage. With the rapid advances in silicon CMOS integrated circuit technology combined with extensive research, a global solutionswhich aims at introducing a global communication system that encompasses all communication standards appears to be emerging. State of the art CMOS technology not only has the capability of operation in the GHz range, but it also provides the advantage of low cost and high level of integration. These features propel CMOS technology as the ideal candidate for current trends, which currently aim to integrate more RF/MW circuits on the same chip. Armed with such technology ideas such as software radio look more attainable than they ever were in the past. Unfortunately, realizing true software radio for mobile applications still remains a tremendous challenge since it requires a high sampling rate and a wide-bandwidth Analog-to-Digital converter which is extremely power hungry and not suitable for battery operated mobile devices. Another approach to realize a flexible and reconfigurable RF/MW transceiver that could operate in a diverse mobile environment and provides a multiband and multistandard solution. The work presented in this thesis focuses on the design of an integrated and tunable low-noise amplifier as part of software defined radio (SDR).

Aujourd'hui, les nouveaux appareils électroniques de télécommunications tendent toujours à plus d'innovations, plus de services et le tout dans de faibles dimensions. Face à un nombre de standards toujours croissant, les nouvelles antennes associées doivent être capables de couvrir plusieurs bandes de fréquences avec des caractéristiques de rayonnement variées, en un minimum d'encombrement. Cette thèse a permis la conception de plusieurs antennes combinées à polarisations multiples pour les applications spatiales. À partir d'un état de l'art d'antennes de géométries variées et devant la complexité de disposer de plusieurs types de polarisations au sein d'un même élément, l'étude a été divisée en deux parties. La première présente en particulier une antenne quadribande fonctionnant en polarisation linéaire pour les standards Bluetooth et WLAN. Sa géométrie consiste en un élément de fine épaisseur, replié en forme de U, entouré d'une cavité cylindrique. La seconde partie propose plusieurs antennes bibandes en polarisation circulaire, basées sur le principe d'éléments imprimés carrés à coins coupés: une antenne monocouche pour les standards GPS-SDARS et une antenne bicouche dédiée aux deux bandes de fréquences GPS existantes. Au final, en combinant ces différents éléments rayonnants, on obtient des antennes multistandards regroupant les deux types de polarisations, linéaire et circulaire.