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Integrated circuit development is an industry-driven high-risk high-stakes environment. The time from the concept of a new transistor technology to the market-ready product is measured in decades rather than months or years. This increases the risk for any company endeavouring on the journey of driving a new concept. Additionally to the return on investment being in the far future, it is only to be expected at all in high volume production, increasing the upfront investment. What makes the undertaking worthwhile are the exceptional gains that are to be expected, when the production reaches the market and enables better products. For these reasons, the adoption of new transistor technologies is usually based on small increments with foreseeable impact on the production process. Emerging semiconductor device development must be able to prove its value to its customers, the chip-producing industry, the earlier the better. With this thesis, I provide a new approach for early evaluation of emerging reconfigurable transistors in reconfigurable digital circuits. Reconfigurable transistors are a type of MOSFET that features a controllable conduction polarity, i.e., they can be configured by other input signals to work as PMOS or NMOS devices. Early device and circuit characterisation poses some challenges that are currently largely neglected by the development community. Firstly, to drive transistor development into the right direction, early feedback is necessary, which requires a method that can provide quantitative and qualitative results over a variety of circuit designs and must run mostly automatic. It should also require as little expert knowledge as possible to enable early experimentation on the device and new circuit designs together. Secondly, to actually run early, its device model should need as little data as possible to provide meaningful results. The proposed approach of this thesis tackles both challenges and employs model checking, a formal method, to provide a framework for the automated quantitative and qualitative analysis. It pairs a simple transistor device model with a charge transport model of the electrical network. In this thesis, I establish the notion of transistor-level reconfiguration and show the kinds of reconfigurable standard cell designs the device facilitates. Early investigation resulted in the discovery of certain modes of reconfiguration that the transistor features and their application to design reconfigurable standard cells. Experiments with device parameters and the design of improved combinational circuits that integrate new reconfigurable standard cells further highlight the need for a thorough investigation and quantification of the new devices and newly available standard cells. As their performance improvements are inconclusive when compared to established CMOS technology, a design space exploration of the possible reconfigurable standard cell variants and a context-aware quantitative analysis turns out to be required. I show that a charge transport model of the analogue transistor circuit provides the necessary abstraction, precision and compatibility with an automated analysis. Formalised in a DSL, it enables designers to freely characterise and combine parametrised transistor models, circuit descriptions that are device independent, and re-usable experiment setups that enable the analysis of large families of circuit variants. The language is paired with a design space exploration algorithm that explores all implementation variants of a Boolean function that employs various degrees and modes of reconfiguration. The precision of the device models and circuit performance calculations is validated against state-of-the-art FEM and SPICE simulations of production transistors. Lastly, I show that the exploration and analysis can be done efficiently using two important Boolean functions. The analysis ranges from worst-case measures, like delay, power dissipation and energy consumption to the detection and quantification of output hazards and the verification of the functionality of a circuit implementation. It ends in presenting average performance results that depend on the statistical characterisation of application scenarios. This makes the approach particularly interesting for measures like energy consumption, where average results are more interesting, and for asynchronous circuit designs which highly depend on average delay performance. I perform the quantitative analysis under various input and output load conditions in over 900 fully automated experiments. It shows that the complexity of the results warrants an extension to electronic design automation flows to fully exploit the capabilities of reconfigurable standard cells. The high degree of automation enables a researcher to use as little as a Boolean function of interest, a transistor model and a set of experiment conditions and queries to perform a wide range quantitative analyses and acquire early results.:1 Introduction 1.1 Emerging Reconfigurable Transistor Technology 1.2 Testing and Standard Cell Characterisation 1.3 Research Questions 1.4 Design Space Exploration and Quantitative Analysis 1.5 Contribution 2 Fundamental Reconfigurable Circuits 2.1 Reconfiguration Redefined 2.1.1 Common Understanding of Reconfiguration 2.1.2 Reconfiguration is Computation 2.2 Reconfigurable Transistor 2.2.1 Device geometry 2.2.2 Electrical properties 2.3 Fundamental Circuits 3 Combinational Circuits and Higher-Order Functions 3.1 Programmable Logic Cells 3.1.1 Critical Path Delay Estimation using Logical Effort Method 3.1.2 Multi-Functional Circuits 3.2 Improved Conditional Carry Adder 4 Constructive DSE for Standard Cells Using MC 4.1 Principle Operation of Model Checking 4.1.1 Model Types 4.1.2 Query Types 4.2 Overview and Workflow 4.2.1 Experiment setup 4.2.2 Quantitative Analysis and Results 4.3 Transistor Circuit Model 4.3.1 Direct Logic Network Model 4.3.2 Charge Transport Network Model 4.3.3 Transistor Model 4.3.4 Queries for Quantitative Analysis 4.4 Circuit Variant Generation 4.4.1 Function Expansion 5 Quantitative Analysis of Standard Cells 5.1 Analysis of 3-Input Minority Logic Gate 5.1.1 Circuit Variants 5.1.2 Worst-Case Analysis 5.2 Analysis of 3-Input Exclusive OR Gate 5.2.1 Worst-Case Analysis 5.2.2 Functional Verification 5.2.3 Probabilistic Analysis 6 Conclusion and Future Work 6.1 Future Work A Notational conventions B prism-gen Programming Interfaces Bibliography Terms & Abbreviations

As modern microelectronics advances, enormous challenges have to be overcome in order to further increase device performance, enabling highspeed and ultra-low-power applications. With progressive scaling of Silicon MOSFETs, charge carrier mobility has dropped significantly and became a critical device parameter over the last decade. Present technology nodes make use of strain engineering to partially recover this mobility loss. Even though carrier mobility is a crucial parameter for present technology nodes, it cannot be determined accurately by methods typically available in industrial environments. A major objective of this work is to study the magnetoresistance mobility μMR of strained VLSI devices based on a 28 nm ground rule. This technique allows for a more direct access to charge carrier mobility, compared to conventional current/ voltage and capacitance/ voltage mobility derivation methods like the effective mobility μeff, in which series resistance, inversion charge density and effective channel length are necessary to extract the mobility values of the short channel devices. Aside from providing an anchor for accurate μeff measurements in linear operation conditions, μMR opens the possibility to investigate the saturation region of the device, which cannot be accessed by μeff. Electron and hole mobility of nFET and pFET devices with various gate lengths are studied from linear to saturation region. In addition, the interplay between mobility enhancement due to strain improvement, and mobility degradation due to short channel effects with decreasing channel length is analyzed. As a concept device for future nanoelectronic building blocks, silicon nanowire Schottky field-effect transistors are investigated in the second part of this work. These devices exhibit an ambipolar behaviour, which gives the opportunity to measure both electron and hole transport on a single device. The temperature dependence of the source/drain current for specific gate and drain voltages is analyzed within the framework of voltage dependent effective barrier heights.:1. Einleitung 2. Theoretische Grundlagen 3. Charakterisierungsmethoden 4. Messaufbau 5. Ergebnisse der Untersuchungen an MOSFETs 6. Ergebnisse der Untersuchungen an SiNW Transistoren 7. Zusammenfassung Anhang Danksagungen

Silicon nanowire based multiple gate metal oxide field effect transistors(MG-MOSFET) appear as replacements for conventional bulk transistors in post 45nm technology nodes. In such transistors the short channel effect(SCE) is controlled by the device geometry, and hence an undoped (or, lightly doped) ultra-thin body silicon nanowire is used to sustain the channel. The use of undoped body also solves several issues in bulk MOSFETs e.g., random dopant fluctuations, mobility degradation and compatibility with midgap metal gates. The electrostatic integrity of such devices increases with the scaling down of the body thickness. Since the quantization of electron energy cannot be ignored in such ultra-thin body devices, it is extremely important to consider quantum effects in their threshold voltage models. Most of the models reported so far are valid for long channel double gate devices. Only Munteanu et al. [Journal of non-crystalline solids vol 351 pp 1911-1918 2005] have reported threshold voltage model for short channel symmetric double gate MOSFET, however it involves unphysical fitting parameters. Only Munteanu et al.[Molecular simulation vol 31 pp 839-845 2005] reported threshold voltage model for quad gate transistor which is implicit in nature. On the other hand no modeling work has been reported for other types of MG-MOSFETs (e.g., tri gate, cylindrical body)apart from numerical simulation results. In this work we report physically based closed form quantum threshold voltage models for short channel symmetric double gate, quad gate and cylindrical body gate-all-around MOSFETs. In these devices quantum effects aries mainly due to the structural confinement of electron energy. Proposed models are based on the analytical solution of two or three-dimensional Poisson equation and one or two-dimensional Schrodinger equation depending on the device geometries. Judicial approximations have been taken to simplify the models in order to make them closed form and efficient for large scale circuit simulation. Effort has also been put to model the quantum threshold voltage of tri gate MOSFET. However it is found that the energy quantization in tri gate devices are mainly due to electronic confinement and hence it is very difficult to develop closed form analytical equations for the threshold voltage. Thus in this work the modeling of tri gate devices have been limited to long channel cases. All the models are validated against the professional numerical simulator.

Undoped body multi gate (MG) Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are appearing as replacements for single gate bulk MOSFET in forthcoming sub-45nm technology nodes. It is therefore extremely necessary to develop compact models for MG transistors in order to use them in nano-scale integrated circuit design and simulation. There is however a sharp distinction between the electrostatics of traditional bulk transistors and undoped body devices. In bulk transistor, where the substrate is sufficiently doped, the inversion charges are located close to the surface and hence the surface potential solely controls the electrostatic integrity of the device. However, in undoped body devices, gate electric field penetrates the body center, and inversion charge exists throughout the body. In contrast to the bulk transistors, depending on device geometry, the potential of the body center of undoped body devices could be higher than the surface in weak inversion regime and the current flows through the center-part of the device instead of surface. Several crucial parameters (e.g. Sub-threshold slope) sometimes become more dependable on the potential of body center rather than the surface. Hence the body-center potential should also be modeled correctly along with the surface-potential for accurate calculation of inversion charge, threshold voltage and other related parameters of undoped body multi-gate transistors. Although several potential models for MG transistors have been proposed to capture the short channel behavior in the subthreshold regime but most of them are based on the crucial approximation of coverting the 2D Poisson’s equation into Laplace equation. This approximation holds good only at surface but breaks down at body center and in the moderate inversion regime. As a result all the previous models fail to capture the potential of body center Correctly and remain valid only in weak-inversion regime. In this work we have developed semiclassical compact models for potential distribution for double gate (DG) and cylindrical Gate-All-Around (GAA) transistors. The models are based on the analytical solution of 2D Poisson’s equation in the channel region and valid for both: a) weak and strong inversion regimes, b) long channel and short channel transistors, and, c) body surface and center. Using the proposed model, for the first time, it is demonstrated that the body potential versus gate voltage characteristics for the devices having equal channel lengths but different body thicknesses pass through a single common point (termed as crossover point). Using the concept of “crossover point” the effect of body thickness on the threshold voltage of undoped body multi-gate transistors is explained. Based on the proposed body potential model, a new compact model for the subthreshold swing is formulated. Some other parameters e.g. inversion charge, threshold voltage roll-off etc are also studied to demonstrate the impact of body center potential on the electrostatics of multi gate transistor. All the models are validated against professional numerical device simulator.