Restoring vision to the blind has been an objective of several research teams for a number of years. It is known that spots of light -- phosphenes -- can be elicited by way of electrical stimulation of surviving retinal neurons. Beyond this, however, our understanding of prosthetic vision remains rudimentary. To advance the realisation of a clinically viable prosthesis for the blind, a versatile integrated circuit neurostimulator was designed, manufactured, and verified. The neurostimulator provides electrical stimuli to surviving neurons in the visual pathway, affording blind patients some form of patterned vision; besides other benefits (independence), this limited vision would let patients distinguish between day and night (resetting their circadian rhythm). This thesis presents the development of the neurostimulator, an interdisciplinary work bridging engineering and medicine. Features of the neurostimulator include: high-voltage CMOS transistors in key circuits, to prevent voltage compliance issues due to an unknown or changing combined tissue and electrode/tissue interface impedance; simultaneous stimulation using current sources and sinks, with return electrodes configured to provide maximum charge containment at each stimulation site; stimuli delivered to a two dimensional mosaic of hexagonally packed electrodes, multiplexing current sources and sinks to allow each electrode in the whole mosaic to become a stimulation site; electrode shorting to remove excess charge accumulated during each stimulation phase. Detailed electrical testing and characterisation verified that the neurostimulator performed as specified, and comparable to, or better than, other vision prostheses neurostimulators. In addition, results from several animal experiments verified that the neurostimulator can elicit electrically evoked visual responses. The features of the neurostimulator enable research into how simultaneous electrical stimulation affects the visual neural pathways; those research results could impact other neural prosthetics research and devices.

Restoring vision to the blind has been an objective of several research teams for a number of years. It is known that spots of light -- phosphenes -- can be elicited by way of electrical stimulation of surviving retinal neurons. Beyond this, however, our understanding of prosthetic vision remains rudimentary. To advance the realisation of a clinically viable prosthesis for the blind, a versatile integrated circuit neurostimulator was designed, manufactured, and verified. The neurostimulator provides electrical stimuli to surviving neurons in the visual pathway, affording blind patients some form of patterned vision; besides other benefits (independence), this limited vision would let patients distinguish between day and night (resetting their circadian rhythm). This thesis presents the development of the neurostimulator, an interdisciplinary work bridging engineering and medicine. Features of the neurostimulator include: high-voltage CMOS transistors in key circuits, to prevent voltage compliance issues due to an unknown or changing combined tissue and electrode/tissue interface impedance; simultaneous stimulation using current sources and sinks, with return electrodes configured to provide maximum charge containment at each stimulation site; stimuli delivered to a two dimensional mosaic of hexagonally packed electrodes, multiplexing current sources and sinks to allow each electrode in the whole mosaic to become a stimulation site; electrode shorting to remove excess charge accumulated during each stimulation phase. Detailed electrical testing and characterisation verified that the neurostimulator performed as specified, and comparable to, or better than, other vision prostheses neurostimulators. In addition, results from several animal experiments verified that the neurostimulator can elicit electrically evoked visual responses. The features of the neurostimulator enable research into how simultaneous electrical stimulation affects the visual neural pathways; those research results could impact other neural prosthetics research and devices.

This dissertation presents the system architecture and implementation of two wireless systems-on-chip (SoCs) for diagnostics and treatment of neurological disorders. It also validates the SoCs as an electronic implant for preoperative monitoring and treatment of intractable epilepsy. The first prototype SoC is a neural recording interface intended for wireless monitoring of intractable epilepsy. The 0.13um CMOS SoC has 64 recording channels, 64 programmable FIR filters and an integrated 915MHz FSK PLL-based wireless transmitter. Each channel contains a low-noise amplifier and a modified 8-bit SAR ADC that and can provide analog-digital multiplication by modifying the ADC sampling phase. It is used in conjunction with 12-bit digital adders and registers to implement 64 16-tap FIR filters with a minimal area and power overhead. In vivo measurement results from freely moving rodents demonstrate its utility in preoperative monitoring epileptic seizures. Treatment of intractable epilepsy by responsive neurostimulation requires seizure detection capabilities. Next, a low-power VLSI processor architecture for early seizure detection is described. It the magnitude, phase and phase synchronization of two neural signals - all precursors of a seizure. The processor is utilized in an implantable responsive neural stimulator application. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The efficacy of the processor in epileptic seizure detection is validated on human EEG data and yields comparable performance to software-based algorithms. The second prototype SoC is a closed-loop 64-channel neural stimulator that includes the aforementioned seizure detector processor and is used for preventive seizure abortion. It constitutes a neural vector analyzer that monitors the magnitude, phase and phase synchronization of neural signals to enable seizure detection. In a closed loop, abnormal phase synchrony triggers the programmable-waveform biphasic neural stimulator. To implement these functionalities, the 0.13um CMOS SoC integrates 64 amplifiers with switched-capacitor (SC) bandpass filters, 64 MADCs, 64 16-tap FIR filters, a processor, 64 biphasic stimulators and a wireless transmitter. The SoC is validated in the detection and abortion of seizures in freely moving rodents on-line and in early seizure detection in humans off-line. The results demonstrate its utility in treatment of intractable epilepsy.

This dissertation presents the system architecture and implementation of two wireless systems-on-chip (SoCs) for diagnostics and treatment of neurological disorders. It also validates the SoCs as an electronic implant for preoperative monitoring and treatment of intractable epilepsy. The first prototype SoC is a neural recording interface intended for wireless monitoring of intractable epilepsy. The 0.13um CMOS SoC has 64 recording channels, 64 programmable FIR filters and an integrated 915MHz FSK PLL-based wireless transmitter. Each channel contains a low-noise amplifier and a modified 8-bit SAR ADC that and can provide analog-digital multiplication by modifying the ADC sampling phase. It is used in conjunction with 12-bit digital adders and registers to implement 64 16-tap FIR filters with a minimal area and power overhead. In vivo measurement results from freely moving rodents demonstrate its utility in preoperative monitoring epileptic seizures. Treatment of intractable epilepsy by responsive neurostimulation requires seizure detection capabilities. Next, a low-power VLSI processor architecture for early seizure detection is described. It the magnitude, phase and phase synchronization of two neural signals - all precursors of a seizure. The processor is utilized in an implantable responsive neural stimulator application. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The efficacy of the processor in epileptic seizure detection is validated on human EEG data and yields comparable performance to software-based algorithms. The second prototype SoC is a closed-loop 64-channel neural stimulator that includes the aforementioned seizure detector processor and is used for preventive seizure abortion. It constitutes a neural vector analyzer that monitors the magnitude, phase and phase synchronization of neural signals to enable seizure detection. In a closed loop, abnormal phase synchrony triggers the programmable-waveform biphasic neural stimulator. To implement these functionalities, the 0.13um CMOS SoC integrates 64 amplifiers with switched-capacitor (SC) bandpass filters, 64 MADCs, 64 16-tap FIR filters, a processor, 64 biphasic stimulators and a wireless transmitter. The SoC is validated in the detection and abortion of seizures in freely moving rodents on-line and in early seizure detection in humans off-line. The results demonstrate its utility in treatment of intractable epilepsy.