Ferroelectric field effect transistor (FeFET) memories based on a new type of ferroelectric material (silicon doped hafnium oxide) were studied within the scope of the present work. Utilisation of silicon doped hafnium oxide (Si:HfO2) thin films instead of conventional perovskite ferroelectrics as a functional layer in FeFETs provides compatibility to the CMOS process as well as improved device scalability. The influence of different process parameters on the properties of Si:HfO2 thin films was analysed in order to gain better insight into the occurrence of ferroelectricity in this system. A subsequent examination of the potential of this material as well as its possible limitations with the respect to the application in non-volatile memories followed. The Si:HfO2-based ferroelectric transistors that were fully integrated into the state-of-the-art high-k metal gate CMOS technology were studied in this work for the first time. The memory performance of these devices scaled down to 28 nm gate length was investigated. Special attention was paid to the charge trapping phenomenon shown to significantly affect the device behaviour.:1 Introduction 2 Fundamentals 2.1 Non-volatile semiconductor memories 2.2 Emerging memory concepts 2.3 Ferroelectric memories 3 Characterisation methods 3.1 Memory characterisation tests 3.2 Ferroelectric memory specific characterisation tests 3.3 Trapping characterisation methods 3.4 Microstructural analyses 4 Sample description 4.1 Metal-insulator-metal capacitors 4.2 Ferroelectric field effect transistors 5 Stabilisation of the ferroelectric properties in Si:HfO2 thin films 5.1 Impact of the silicon doping 5.2 Impact of the post-metallisation anneal 5.3 Impact of the film thickness 5.4 Summary 6 Electrical properties of the ferroelectric Si:HfO2 thin films 6.1 Field cycling effect 6.2 Switching kinetics 6.3 Fatigue behaviour 6.4 Summary 7 Ferroelectric field effect transistors based on Si:HfO2 films 7.1 Effect of the silicon doping 7.2 Program and erase operation 7.3 Retention behaviour 7.4 Endurance properties 7.5 Impact of scaling on the device performance 7.6 Summary 8 Trapping effects in Si:HfO2-based FeFETs 8.1 Trapping kinetics of the bulk Si:HfO2 traps 8.2 Detrapping kinetics of the bulk Si:HfO2 traps 8.3 Impact of trapping on the FeFET performance 8.4 Modified approach for erase operation 8.5 Summary 9 Summary and Outlook

Edge computing requires highly energy efficient microprocessor units with embedded non-volatile memories to process data at IoT sensor nodes. Ferroelectric non-volatile memory devices are fast, low power and high endurance, and could greatly enhance energy-efficiency and allow flexibility for finer grain logic and memory. This paper will describe the basics of ferroelectric devices for both hysteretic (non-volatile memory) and negative capacitance (steep slope switch) devices, and then project how these can be used in low-power logic cell architectures and fine-grain logic-in-memory (LiM) circuits.

Nanokristalle werden beispielsweise für eine Anwendung in Solarzellen, Lichtemittern und nichtflüchtigen Datenspeichern diskutiert. Damit diese Anwendungen funktionieren können, ist eine genaue Kontrolle der Kristallitgröße sowie der Flächendichte und Lage der Kristallite in der Matrix wichtig. Zudem sollte die Matrix amorph sein, da amorphe Matrixmaterialien die Nanokristall-Oberfläche besser passivieren und beständiger gegen Leckströme sind. In dieser Arbeit werden Ge-Nanokristalle in die Hoch-Epsilon-Dielektrika ZrO2 und TaZrOx eingebettet. Im System Ge/ZrO2 kristallisieren die Ge-Cluster und die ZrO2-Matrix bei der gleichen Temperatur. Aufgrund der kristallinen Matrix weicht die Form der Ge-Nanokristalle von einer Kugel ab, worunter unter anderem die Größenkontrolle leidet. Die Beimischung von Ta2O5 stabilisiert die amorphe Phase des ZrO2 und verhindert dadurch die gemeinsame Kristallisation. Dadurch wird es im System Ge/TaZrOx möglich, kugelförmige Ge-Nanokristalle im Größenbereich von 3 nm bis 6 nm positionskontrolliert in eine amorphe Matrix einzubetten. Für die Untersuchung einer möglichen Anwendung des Materialsystems wurden Speicherzellen eines nichtflüchtigen Datenspeichers auf Basis von Ge-Nanokristallen hergestellt. Dabei zeigte sich, dass das System Ge/TaZrOx überdurchschnittlich viele Ladungen speichert und daher für diese Anwendung vielversprechend ist. Zudem stabilisiert die Beimischung von Ta2O5 eine extrem seltene orthorhombische Modifikation des ZrO2. Für ferroelektrische Datenspeicher könnte diese Phase eine aussichtsreiche Alternative zum HfO2 sein.

In an era in which the amount of produced and stored data continues to exponentially grow, standard memory concepts start showing size, power consumption and costs limitation which make the search for alternative device concepts essential. Within a context where new technologies such as DRAM, magnetic RAM, resistive RAM, phase change memories and eFlash are explored and optimized, ferroelectric memory devices like FeRAM seem to showcase a whole range of properties which could satisfy market needs, offering the possibility of creating a non-volatile RAM. In fact, hafnia and zirconia-based ferroelectric materials opened up a new scenario in the memory technology scene, overcoming the dimension scaling limitations and the integration difficulties presented by their predecessors perovskite ferroelectrics. In particular, HfₓZr₁₋ₓO₂ stands out because of high processing flexibility and ease of integration in the standard semiconductor industry process flows for CMOS fabrication. Nonetheless, further understanding is necessary in order tocorrelate device performance and reliability to the establishment of ferroelectricity itself. The aim of this work is to investigate how the composition of the ferroelectric oxide, together with the one of the electrode materials influence the behavior of a ferroelectric RAM. With this goal, different process parameters and reliability properties are considered and an analysis of the polarization reversal is performed. Starting from undoped hafnia and zirconia and subsequently examining their intermixed system, it is shown how surface/volume energy contributions, mechanical stress and oxygen-related defects all concur in the formation of the ferroelectric phase. Based on the process optimization of an HfₓZr₁₋ₓO₂-based capacitor performed within these pages, a 64 kbit 1T1C FeRAM array is demonstrated by Sony Semiconductor Solutions Corporation which shows write voltage and latency as low as 2.0 V and 16 ns, respectively. Outstanding retention and endurance performances are also predicted, which make the addressed device an extremely strong competitor in the semiconductor scene.

The new class of fully silicon-compatible hafnia-based ferroelectrics with high switchable polarization and good endurance and thickness scalability shows a strong promise for new generations of logic and memory devices. Among other factors, their competitiveness depends on the power efficiency that requires reliable low-voltage operation. Here, we show genuine ferroelectric switching in HfₓZr₍₁₋ₓ₎ O₂ (HZO) layers in the application-relevant capacitor geometry, for driving signals as low as 800 mV and coercive voltage below 500 mV. Enhanced piezoresponse force microscopy with sub-picometer sensitivity allowed for probing individual polarization domains under the top electrode and performing a detailed analysis of hysteretic switching. The authentic local piezoelectric loops and domain wall movement under bias attest to the true ferroelectric nature of the detected nanodomains. The systematic analysis of local piezoresponse loop arrays reveals a totally unexpected thickness dependence of the coercive fields in HZO capacitors. The thickness decrease from 10 to 7 nm is associated with a remarkably strong decrease of the coercive field, with about 50% of the capacitor area switched at coercive voltages ≤0.5 V. Our explanation consistent with the experimental data involves a change of mechanism of nuclei-assisted switching when the thickness decreases below 10 nm. The practical implication of this effect is a robust ferroelectric switching under the millivolt-range driving signal, which is not expected for the standard coercive voltage scaling law. These results demonstrate a strong potential for further aggressive thickness reduction of HZO layers for low-power electronics.

In this review the different concepts of nanoscale resistive switching memory devices are described and classified according to their I–V behaviour and the underlying physical switching mechanisms. By means of the most important representative devices, the current state of electrical performance characteristics is illuminated in-depth. Moreover, the ability of resistive switching devices to be integrated into state-of-the-art CMOS circuits under the additional consideration with a suitable selector device for memory array operation is assessed. From this analysis, and by factoring in the maturity of the different concepts, a ranking methodology for application of the nanoscale resistive switching memory devices in the memory landscape is derived. Finally, the suitability of the different device concepts for beyond pure memory applications, such as brain inspired and neuromorphic computational or logic in memory applications that strive to overcome the vanNeumann bottleneck, is discussed.