Nowadays, many ASIP systems with high computational capabilities are designed in order to fulfill the increasing demands of technical applications. However, the design of ASIP system usually takes many man hours. Therefore, a number of EDA tools are developed to ease the design effort, but they limit the design freedom due to their predefined design templates. Consequently, designers are forced to use lower level HDLs which offer high design flexibility but require substantial design hours. A novel design automation tool called NoGap was proposed to balance such issues. The NoGap system, which is especially used in ASIPs and accelerator design, effectively provides high design flexibility and saves design effort for designers. The efficiency and design ability of NoGap were investigated in this thesis work. NoGap was used to implement an eight-way SIMD datapath of an ASIP called Sleipnir, which was devised by the Division of Computer Engineering at Linköping University. For contrast, the manually crafted HDL implementation of the Sleipnir was taken. The critical path implementations, done by both design approaches, were synthesized to the Altera Strtix IV FPGA. The synthesize results showed that the NoGap design although used 1.358 times as many hardware units as the original HDL design. Their timing performance is comparable (HDL/NoGap-60.042/58.156Mhz). In this thesis, based on the design experience of SIMD datapath, valuable aspects were suggested to benefit the future users who will use NoGap to implement SIMD structures. In addition, the hidden bugs and insufficient features of NoGap were discovered, and the referable suggestions were provided in order to help the developers to improve the NoGap system.

Nowadays, hardware designers want to get a powerful and friendly tool to speedup the design flow and design quality. The new development suit NoGap is pro-posed to meet those requirements. NoGap is a design automation tool for ASIP,it helps users to focus on the design stage, free them from module connection andsignal assignment, or integration. Different from the normal ADL tools which limitusers’ design ideas to some template frameworks, NoGap allow designers to im-plement what they want with NoGap Common Language (NoGapCL). However,NoGap is still not perfect, some important functionalities are lacking, but withthe flexible generator component structure, NoGap and NoGapCL can easily beextended.This thesis will firstly investigate the structure of Novel Generator of Acceler-ators and Processors (NoGap) from software prospective view, and then present anew NoGap generator, OpCode Assignment Generator (OpAssignGen), which al-lows users to assign operation code values, exclude operation codes and customizethe operation code size or instruction size.A simple example based on the Microprocessor without Interlocked PipelineStages (MIPS) instructions sets will be mentioned to give users a brief view ofhow to use OpAssignGen. After that, the implementation of the new generatorwill be explained in detail.What’s more, some of NoGap’s flaws will be exposed, but more suggestionsand improvements for NoGap will be given.At last, a successful synthesis result based on the simple MIPS hardware im-plementation will be shown to prove the new generator is well implemented. Moreresults and the final conclusion will be given at the end of the thesis.

<p>The need for a more general hardware description language aimed specifically at processors, and vague notions and visions of how that language would be realized, lead to this thesis. The aim was to use the visions and initial ideas to evolve and formalize a language and begin implementing the tools to use it. The language, called NoGAP Common Language, is designed to give the programmer freedom to implement almost any processor design without being encumbered by many of the tedious tasks normally present in the creation process. While evolving the language it was chosen to borrow syntaxes from C++ and verilog to make the code and concepts easy to understand. The main advantages of NoGAP Common Language compared to RTL languages are;</p><p>-the ability to define the data paths of instructions separate from each other and have them merged automatically along with assigned timings to form the pipeline.</p><p>-having control paths automatically routed by activating named clauses of code coupled to control signals.</p><p>-being able to specify a decoder, where the instructions and control structures are defined, that control signals are routed to.</p><p>The implemented compiler was created with C++, Bison, and Flex and utilizes an AST structure, a symbol table, and a connection graph. The AST is traversed by several functions to generate the connection graph where the instructions of the processor can be merged into a pipeline. The compiler is in the early stages of development and much is left to do and solve. It has become clear though that the concepts of NoGAP Common Language can be implemented and are not just visions.</p> / <p>Behovet av ett mer generellt hårdvarubeskrivande språk specialiseret för processorer och visioner om ett sådant gav upphov till detta examensarbete. Målet var att utveckla visionerna, formalisera dem till ett fungerande språk och börja implementera dess verktyg. Språket, som kallas NoGAP Common Language, är designat för att ge programmeraren friheten att implementera nästan vilken processordesign som helst utan att bli nedtyngd av många av de enformiga uppgifter som annars måste utföras. Under utvecklingsprocessen valdes det att låna många syntax från C++ och verilog för att göra språket lätt att förstå och känna igen för många. De största fördelarna med att utveckla i NoGAP Common Language jämfört</p><p>med vanliga RTL språk som verilog är; </p><p>-att kunna specificera datavägar för instruktioner separat från varandra och få dem automatiskt förenade med hjälp av tidsangivelser till en pipeline.</p><p>-att få kontrollvägar automatiskt dragna genom att aktivera namngivna klausuler med kod kopplade till kontrollsignaler. </p><p>-att kunna specifiera en avkodare som kontrollvägarna kan kopplas till där</p><p>kodning för instruktioner kan anges. </p><p>Kompilatorn som implementerats med C++, Bison och Flex använder sig av en AST struktur, en symboltabell och en signalvägsgraf. AST strukturen traverseras av flera funktioner som bygger upp signalvägsgrafen där processorns instruktioner förenas till en pipeline. Utvecklingen av kompilatorn är ännu bara i de första stadierna och mycket är kvar att göra och lösa. Det har dock blivit klart att det är möjligt att implementera koncepten i NoGAP Common Language och att de inte bara är lösa visioner. </p>

A Control Data Flow Graph (CDFG) is a Directed Acyclic Graph (DAG) in which a node can be either an operation node or a control node. The target of this kind of graph is to capture allt he control and data flow information of the original hardware description while preserving the various dependencies. This kind of graph is generated by Novel Generator of Accelerators and Processors (NoGap), a design automation tool for Application Specific Instruction-set Processor (ASIP) and accelerator design developed by Per Karlström from the Department of Electrical Engineering of Linköping University. The aim of this project is to validate the graph, check if it fulfills the requirements of its definition. If it does not, it is considered an error and the running process will be aborted. Moreover, useful information will be extracted from the graph for futute work.

The need for a more general hardware description language aimed specifically at processors, and vague notions and visions of how that language would be realized, lead to this thesis. The aim was to use the visions and initial ideas to evolve and formalize a language and begin implementing the tools to use it. The language, called NoGAP Common Language, is designed to give the programmer freedom to implement almost any processor design without being encumbered by many of the tedious tasks normally present in the creation process. While evolving the language it was chosen to borrow syntaxes from C++ and verilog to make the code and concepts easy to understand. The main advantages of NoGAP Common Language compared to RTL languages are; -the ability to define the data paths of instructions separate from each other and have them merged automatically along with assigned timings to form the pipeline. -having control paths automatically routed by activating named clauses of code coupled to control signals. -being able to specify a decoder, where the instructions and control structures are defined, that control signals are routed to. The implemented compiler was created with C++, Bison, and Flex and utilizes an AST structure, a symbol table, and a connection graph. The AST is traversed by several functions to generate the connection graph where the instructions of the processor can be merged into a pipeline. The compiler is in the early stages of development and much is left to do and solve. It has become clear though that the concepts of NoGAP Common Language can be implemented and are not just visions. / Behovet av ett mer generellt hårdvarubeskrivande språk specialiseret för processorer och visioner om ett sådant gav upphov till detta examensarbete. Målet var att utveckla visionerna, formalisera dem till ett fungerande språk och börja implementera dess verktyg. Språket, som kallas NoGAP Common Language, är designat för att ge programmeraren friheten att implementera nästan vilken processordesign som helst utan att bli nedtyngd av många av de enformiga uppgifter som annars måste utföras. Under utvecklingsprocessen valdes det att låna många syntax från C++ och verilog för att göra språket lätt att förstå och känna igen för många. De största fördelarna med att utveckla i NoGAP Common Language jämfört med vanliga RTL språk som verilog är; -att kunna specificera datavägar för instruktioner separat från varandra och få dem automatiskt förenade med hjälp av tidsangivelser till en pipeline. -att få kontrollvägar automatiskt dragna genom att aktivera namngivna klausuler med kod kopplade till kontrollsignaler. -att kunna specifiera en avkodare som kontrollvägarna kan kopplas till där kodning för instruktioner kan anges. Kompilatorn som implementerats med C++, Bison och Flex använder sig av en AST struktur, en symboltabell och en signalvägsgraf. AST strukturen traverseras av flera funktioner som bygger upp signalvägsgrafen där processorns instruktioner förenas till en pipeline. Utvecklingen av kompilatorn är ännu bara i de första stadierna och mycket är kvar att göra och lösa. Det har dock blivit klart att det är möjligt att implementera koncepten i NoGAP Common Language och att de inte bara är lösa visioner.

<p>System-on-Chip is increasingly built using ASIP(Application  Specific Instruction set Processor) due to the flexibility and efficiency obtained from ASIPs. NoGAP (Novel Generator of Accelerator and Processor framework) is an innovative approach for  ASIP design, which provides the advantage of both ADL (Architecture  Description Language) and HDL (Hardware Description Language) to the  designer.</p><p>For the processors designed using NoGAP, software tools need to be automatically generated, to aid the  designer in programming and verifying the processor. As part of the master thesis work, we have developed two generators namely Assembler generator and Cycle-Accurate Simulator generator for NoGAP using C++. The Assembler generator automatically generates an assembler, which is used to convert the assembly code written by a programmer into relocatable binary code. The Cycle-Accurate Simulator generator automatically generates a cycle-accurate simulator to model the behavior of the designed processor. Both these generators are static, and can be used to generate the tools for any processor created using NoGAP.</p><p>In this report, we have detailed the concepts behind the generators,and the implementation details of the generators. We have listed the results obtained from running assembler and cycle-accurate simulator on a test processor created using NoGAP.</p> / NoGAP

System-on-Chip is increasingly built using ASIP(Application  Specific Instruction set Processor) due to the flexibility and efficiency obtained from ASIPs. NoGAP (Novel Generator of Accelerator and Processor framework) is an innovative approach for  ASIP design, which provides the advantage of both ADL (Architecture  Description Language) and HDL (Hardware Description Language) to the  designer. For the processors designed using NoGAP, software tools need to be automatically generated, to aid the  designer in programming and verifying the processor. As part of the master thesis work, we have developed two generators namely Assembler generator and Cycle-Accurate Simulator generator for NoGAP using C++. The Assembler generator automatically generates an assembler, which is used to convert the assembly code written by a programmer into relocatable binary code. The Cycle-Accurate Simulator generator automatically generates a cycle-accurate simulator to model the behavior of the designed processor. Both these generators are static, and can be used to generate the tools for any processor created using NoGAP. In this report, we have detailed the concepts behind the generators,and the implementation details of the generators. We have listed the results obtained from running assembler and cycle-accurate simulator on a test processor created using NoGAP. / NoGAP