Currently, on the Internet we can see most of the time clasic website that offer multimedia content to users in the form of texts, pictures and videos or favorite e-shops to enable the purchase of various goods from the comfort of home. More and more we can see website sites, or applications that provide the user with a specific service. This thesis describes a new modern approaches for creating web sites and applications using the latest version of the markup language HTML, which is HTML5. The work is primarily intended for Web developers and encoders, which should provide an overview and basic information in the field of web applications. The acquired knowledge would be to simplify and streamline the work and especially to save time, which can undo web users in the form of new features. The result of their work can be faster, more comfortable user web application (website) that fully exploit potential of web browsers.

Master's thesis proposes a new operation state of distribution network 22kV in Prostějov district after connection of the new Prostějov – Západ substation. The PASS DAISY OFF-LINE Bizon program is used to calculate power losses, optimal network possibilities, as well as to create a new model of Prostějov district's distribution network and to design a modification of a current state of given location. A description of this calculating and simulation program is also included in this paper. The theoretical part describes calculating methods of distribution network’s condition, with emphasis on mathematical method used by PASS DAISY OFF-LINE Bizon program, the modified Newton-Raphson method. The aim of this paper is to prepare technical documentation for E.ON company, with respect to new operation disconnection, planned overhead and cable lines of corresponding parameters. These changes in network's configuration will cause a new distribution of feeding areas. As a result, related changes of provided power from individual feeding points and changes of power currents in electric lines will occur. Due to new operation connection, a reduction of losses and, simultaneously, an improvement of voltage ratios are expected. One of the aims of this paper is to update network's model in PASS DAISY OFF-LINE Bizon program to match the current network’s state of a given area. The outcome of this work is a comparison between the current condition and the new operation condition, with new Prostějov – Západ substation connected, from perspective of distribution network's operator.

Les réseaux-sur-puces (NoCs) utilisés dans les architectures multiprocesseurs-sur-puces posent des défis importants aux approches d'ordonnancement temps réel en ligne (dynamique) et hors-ligne (statique). Un NoC contient un grand nombre de points de contention potentiels, a une capacité de bufferisation limitée et le contrôle réseau fonctionne à l'échelle de petits paquets de données. Par conséquent, l'allocation efficace de ressources nécessite l'utilisation des algorithmes da faible complexité sur des modèles de matériel avec un niveau de détail sans précédent dans l'ordonnancement temps réel. Nous considérons dans cette thèse une approche d'ordonnancement statique sur des architectures massivement parallèles (Massively parallel processor arrays ou MPPAs) caractérisées par un grand nombre (quelques centaines) de c¿urs de calculs. Nous identifions les mécanismes matériels facilitant l'analyse temporelle et l'allocation efficace de ressources dans les MPPAs existants. Nous déterminons que le NoC devrait permettre l'ordonnancement hors-ligne de communications, d'une manière synchronisée avec l'ordonnancement de calculs sur les processeurs. Au niveau logiciel, nous proposons une nouvelle méthode d'allocation et d'ordonnancement capable de synthétiser des ordonnancements globaux de calculs et de communications couvrants toutes les ressources d'exécution, de communication et de la mémoire d'un MPPA. Afin de permettre une utilisation efficace de ressources du matériel, notre méthode prend en compte les spécificités architecturales d'un MPPA et implémente des techniques d'ordonnancement avancées comme la préemption pré-calculée de transmissions de données. Nous avons évalué n / On-chip networks (NoCs) used in multiprocessor systems-on-chips (MPSoCs) pose significant challenges to both on-line (dynamic) and off-line (static) real-time scheduling approaches. They have large numbers of potential contention points, have limited internal buffering capabilities, and network control operates at the scale of small data packets. Therefore, efficient resource allocation requires scalable algorithms working on hardware models with a level of detail that is unprecedented in real-time scheduling. We consider in this thesis a static scheduling approach, and we target massively parallel processor arrays (MPPAs), which are MPSoCs with large numbers (hundreds) of processing cores. We first identify and compare the hardware mechanisms supporting precise timing analysis and efficient resource allocation in existing MPPA platforms. We determine that the NoC should ideally provide the means of enforcing a global communications schedule that is computed off-line (before execution) and which is synchronized with the scheduling of computations on processors. On the software side, we propose a novel allocation and scheduling method capable of synthesizing such global computation and communication schedules covering all the execution, communication, and memory resources in an MPPA. To allow an efficient use of the hardware resources, our method takes into account the specificities of MPPA hardware and implements advanced scheduling techniques such as pre-computed preemption of data transmissions. We evaluate our technique by mapping two signal processing applications, for which we obtain good latency, throughput, and resource use figures.

No description available.

In this thesis, improved techniques for biomolecule analysis using capillary electrophoresis (CE) and matrix-assisted laser desorption/ionization-mass spectrometry (MALDI-MS) and hyphenations between those have been presented.A pre-concentration method which is possible to apply in both techniques, has also been investigated. In this work the off-line MS mode has been used either in the form of fractionation (Paper I) or by incorporating the MALDI target in the CE separation system (Paper II).In Paper I, a protocol for CE-MALDI analysis of cyanogen bromide digested bacteriorhodopsin (BR) peptides as model integral membrane protein peptides were established. Also, an improved protocol for partially automated manufacturing of a concentration MALDI-target plate is presented. The design of the targets was suitable for the fractions from the CE. A novel technique for the integration of CE to MALDI-MS using a closed-open-closed system is presented in Paper II, where the open part is a micro canal functioning as a MALDI target window. A protein separation was obtained and detected with MALDI-MS analysis in the micro canal. A method has been developed for detection of monosaccharides originating from hydrolysis of a single wood fiber performed in a micro channel, with an incorporated electromigration pre-concentration step preceding CE analysis in Paper III. The pre-concentration showed to be highly complex due to the fact that several parameters are included that affecting each other. In Paper IV a protocol using enzymatic digestion, MALDI-TOF-MS and CE with laser induced fluorescence (LIF) detection for the investigation of the degree of substitution of fluorescein isothiocyanate (FITC) to bovine serum albumin (BSA), as a contact allergen model system for protein-hapten binding in the skin, is presented. The intention of a further CE-MALDI hyphenation has been considered during the work. In Paper V 2,6-dihydroxyacetophenone (DHAP) was investigated, showing promising MALDI-MS matrix properties for hydrophobic proteins and peptides. 2,5-dihydroxybenzoic acid (DHB) was undoubtedly the better matrix for the hydrophilic proteins, but its performance for the larger and hydrophobic peptides was not optimal. Consequently, DHAP can be used as a compliment matrix for improved analysis of hydrophobic analytes. / QC 20101214

Si on veut assurer de fawn efficace les tests de conception, de fabrication, de maintenance et le test accompli au cours de l'application pour les systemes electroniques, on est amend a integrer le test hors-ligne et le test en-ligne dans des circuits. Ensuite, pour que les systemes complexes tirent profit des deux types de tests, une telle unification doit etre &endue du niveau circuit aux niveaux carte et module. D'autre part, bien que rintegration des techniques de test hors-ligne et en-ligne fait qu'il est possible de concevoir des systemes pour toute application securitaire, le materiel ajoute pour assurer une haute siirete de fonctionnement fait que la fiabilite de ces systemes est reduite, car la probabilite d'occurrence de fautes augmente. Confront& a ces deux aspects antagoniques, cette these se fixe l'objectif de trouver un compromis entre la securite et la fiabilite de systemes electroniques complexes. Ainsi, dans un premier temps, on propose une solution aux problemes de test hors-ligne et de diagnostic qui se posent dans les &apes intermediaires de revolution vers les cartes 100% compatibles avec le standard IEEE 1149.1 pour le test "boundary scan". Une approche pour le BIST ("Built-In Self-Test") des circuits et connexions "boundary scan" illustre ensuite retape ultime du test hors-ligne de cartes. Puis, le schema UBIST ("Unified BIST") - integrant les techniques BIST et "self-checking" pour le test en-ligne de circuits, est combine au standard IEEE 1149.1, afin d'obtenir une strategie de conception en vue du test unifie de connexions et circuits montes sur des cartes et modules. Enfin, on propose un schema tolerant les fautes et base sur la duplication de ces modules securitaires qui assure la competitivite du systeme resultant du point de vue de la fiabilite, tout en gardant sa silrete inherente. / On one hand, if the goal is to ensure that the design validation, the manufacturing and the maintenance testing, along with the concurrent error detection are efficiently performed in electronic systems, one is led to integrate the off-line and the on-line testing into circuits. Then, for complex systems to make profit of these two types of tests, such unification must be extended from the circuit to the board and module levels. On the other hand, although the unification of off-line and on-line testing techniques makes possible the design of systems suiting any safety application, the hardware added for increasing the application safety also decreases the system reliability, since the probability of occurrence of faults increases. Faced to these two antagonist aspects, this thesis aims at finding a compromise between the safety and the reliability of complex electronic systems. Thus, firstly we propose a solution to the off-line test and diagnosis problems found in the intermediate steps in the evolution towards boards which are 100% compliant with the IEEE standard 1149.1 for boundary scan testing. An approach for the BIST (Built-In Self-Test) of boundary scan circuits and interconnects then illustrates the ultimate step in the board off-line testing. Next, the UBIST (Unified BIST) scheme - merging BIST and self-checking capabilities for circuit on-line testing, is combined with the IEEE standard 1149.1, in order to obtain a design strategy for unifying the tests of interconnects and circuits populating boards and modules. Finally, we propose a fault-tolerant scheme based on the duplication of these kind of modules which ensures the competitivity of the resulting system in terms of reliability at the same time as preserving the inherent module safety.

Si on veut assurer de fawn efficace les tests de conception, de fabrication, de maintenance et le test accompli au cours de l'application pour les systemes electroniques, on est amend a integrer le test hors-ligne et le test en-ligne dans des circuits. Ensuite, pour que les systemes complexes tirent profit des deux types de tests, une telle unification doit etre &endue du niveau circuit aux niveaux carte et module. D'autre part, bien que rintegration des techniques de test hors-ligne et en-ligne fait qu'il est possible de concevoir des systemes pour toute application securitaire, le materiel ajoute pour assurer une haute siirete de fonctionnement fait que la fiabilite de ces systemes est reduite, car la probabilite d'occurrence de fautes augmente. Confront& a ces deux aspects antagoniques, cette these se fixe l'objectif de trouver un compromis entre la securite et la fiabilite de systemes electroniques complexes. Ainsi, dans un premier temps, on propose une solution aux problemes de test hors-ligne et de diagnostic qui se posent dans les &apes intermediaires de revolution vers les cartes 100% compatibles avec le standard IEEE 1149.1 pour le test "boundary scan". Une approche pour le BIST ("Built-In Self-Test") des circuits et connexions "boundary scan" illustre ensuite retape ultime du test hors-ligne de cartes. Puis, le schema UBIST ("Unified BIST") - integrant les techniques BIST et "self-checking" pour le test en-ligne de circuits, est combine au standard IEEE 1149.1, afin d'obtenir une strategie de conception en vue du test unifie de connexions et circuits montes sur des cartes et modules. Enfin, on propose un schema tolerant les fautes et base sur la duplication de ces modules securitaires qui assure la competitivite du systeme resultant du point de vue de la fiabilite, tout en gardant sa silrete inherente. / On one hand, if the goal is to ensure that the design validation, the manufacturing and the maintenance testing, along with the concurrent error detection are efficiently performed in electronic systems, one is led to integrate the off-line and the on-line testing into circuits. Then, for complex systems to make profit of these two types of tests, such unification must be extended from the circuit to the board and module levels. On the other hand, although the unification of off-line and on-line testing techniques makes possible the design of systems suiting any safety application, the hardware added for increasing the application safety also decreases the system reliability, since the probability of occurrence of faults increases. Faced to these two antagonist aspects, this thesis aims at finding a compromise between the safety and the reliability of complex electronic systems. Thus, firstly we propose a solution to the off-line test and diagnosis problems found in the intermediate steps in the evolution towards boards which are 100% compliant with the IEEE standard 1149.1 for boundary scan testing. An approach for the BIST (Built-In Self-Test) of boundary scan circuits and interconnects then illustrates the ultimate step in the board off-line testing. Next, the UBIST (Unified BIST) scheme - merging BIST and self-checking capabilities for circuit on-line testing, is combined with the IEEE standard 1149.1, in order to obtain a design strategy for unifying the tests of interconnects and circuits populating boards and modules. Finally, we propose a fault-tolerant scheme based on the duplication of these kind of modules which ensures the competitivity of the resulting system in terms of reliability at the same time as preserving the inherent module safety.

Si on veut assurer de fawn efficace les tests de conception, de fabrication, de maintenance et le test accompli au cours de l'application pour les systemes electroniques, on est amend a integrer le test hors-ligne et le test en-ligne dans des circuits. Ensuite, pour que les systemes complexes tirent profit des deux types de tests, une telle unification doit etre &endue du niveau circuit aux niveaux carte et module. D'autre part, bien que rintegration des techniques de test hors-ligne et en-ligne fait qu'il est possible de concevoir des systemes pour toute application securitaire, le materiel ajoute pour assurer une haute siirete de fonctionnement fait que la fiabilite de ces systemes est reduite, car la probabilite d'occurrence de fautes augmente. Confront& a ces deux aspects antagoniques, cette these se fixe l'objectif de trouver un compromis entre la securite et la fiabilite de systemes electroniques complexes. Ainsi, dans un premier temps, on propose une solution aux problemes de test hors-ligne et de diagnostic qui se posent dans les &apes intermediaires de revolution vers les cartes 100% compatibles avec le standard IEEE 1149.1 pour le test "boundary scan". Une approche pour le BIST ("Built-In Self-Test") des circuits et connexions "boundary scan" illustre ensuite retape ultime du test hors-ligne de cartes. Puis, le schema UBIST ("Unified BIST") - integrant les techniques BIST et "self-checking" pour le test en-ligne de circuits, est combine au standard IEEE 1149.1, afin d'obtenir une strategie de conception en vue du test unifie de connexions et circuits montes sur des cartes et modules. Enfin, on propose un schema tolerant les fautes et base sur la duplication de ces modules securitaires qui assure la competitivite du systeme resultant du point de vue de la fiabilite, tout en gardant sa silrete inherente. / On one hand, if the goal is to ensure that the design validation, the manufacturing and the maintenance testing, along with the concurrent error detection are efficiently performed in electronic systems, one is led to integrate the off-line and the on-line testing into circuits. Then, for complex systems to make profit of these two types of tests, such unification must be extended from the circuit to the board and module levels. On the other hand, although the unification of off-line and on-line testing techniques makes possible the design of systems suiting any safety application, the hardware added for increasing the application safety also decreases the system reliability, since the probability of occurrence of faults increases. Faced to these two antagonist aspects, this thesis aims at finding a compromise between the safety and the reliability of complex electronic systems. Thus, firstly we propose a solution to the off-line test and diagnosis problems found in the intermediate steps in the evolution towards boards which are 100% compliant with the IEEE standard 1149.1 for boundary scan testing. An approach for the BIST (Built-In Self-Test) of boundary scan circuits and interconnects then illustrates the ultimate step in the board off-line testing. Next, the UBIST (Unified BIST) scheme - merging BIST and self-checking capabilities for circuit on-line testing, is combined with the IEEE standard 1149.1, in order to obtain a design strategy for unifying the tests of interconnects and circuits populating boards and modules. Finally, we propose a fault-tolerant scheme based on the duplication of these kind of modules which ensures the competitivity of the resulting system in terms of reliability at the same time as preserving the inherent module safety.

Submitted by Geandra Rodrigues (geandrar@gmail.com) on 2018-01-08T12:01:24Z No. of bitstreams: 1 guilhermemárciosoares.pdf: 24810934 bytes, checksum: d538ec8cfbd6bb9363a5aa07343bda48 (MD5) / Approved for entry into archive by Adriana Oliveira (adriana.oliveira@ufjf.edu.br) on 2018-01-22T18:36:09Z (GMT) No. of bitstreams: 1 guilhermemárciosoares.pdf: 24810934 bytes, checksum: d538ec8cfbd6bb9363a5aa07343bda48 (MD5) / Made available in DSpace on 2018-01-22T18:36:10Z (GMT). No. of bitstreams: 1 guilhermemárciosoares.pdf: 24810934 bytes, checksum: d538ec8cfbd6bb9363a5aa07343bda48 (MD5) Previous issue date: 2017-11-18 / CAPES - Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / Este documento apresenta uma nova técnica para a minimização da ondulação de baixa frequência, típica de conversores para o acionamento de LEDs alimentados a partir da rede elétrica. Esta estratégia baseia-se na modulação em baixa frequência da razão cíclica do conversor de modo que a ondulação de corrente possa ser reduzida e, consequentemente, as capacitâncias de filtragem do conversor possam ser minimizadas. Esta técnica foi desenvolvida para a aplicação em conversores de malha única, como é o caso de conversores de estágio único ou mesmo dois estágios integrados. A modulação da razão cíclica é projetada de maneira que o comportamento de baixa frequência das principais variáveis do conversor seja alterado, permitindo uma redução da ondulação da corrente de saída ao custo de um incremento cotrolado no conteúdo harmônico da corrente de entrada. Duas possíveis metodologias para a implementação da técnica proposta são discutidas ao longo do trabalho. A primeira envolve a injeção de harmônicas específicas no sinal da razão cíclica do conversor através de ramos adicionais na estrutura de controle. Esta abordagem foi aplicada para projetar um controlador de LEDs baseado em um conversor flyback e também em uma topologia integrada baseada na conexão cascata de dois conversores Buck-boost. Este estudo inicial foi expandido para outros conversores e uma análise generalizada acerca da influência da modulação da razão cíclica no comportamento de controladores de LED alimentados a partir da rede elétrica é apresentada. A segunda metodologia para a implementação da compensação ativa da ondulação de baixa frequência do conversor é baseada na otimização de um controlador proporcional-integral a fim de que tal elemento influencie não só no comportamento dinâmico do circuito, mas também na característica de baixa frequência do conversor. Por fim são discutidas as principais contribuições da tese e algumas propostas para trabalhos futuros são apresentadas / This document presents a novel approach for low-frequency output current ripple minimization in off-line light-emitting diode (LED) drivers. This strategy is based on the large-signal modulation of the duty-cycle so that the output ripple can be reduced and, consequently, the required filtering capacitances of the converter can be somehow decreased. This technique is devised to be used on converters in which a single control loop is employed, such as off-line single-stage or integrated converters. The duty-cycle modulation is used to change the shape of the main waveforms of the converter, especially the input and output currents. This allows for a reduction of the output current peak-to-peak ripple while the harmonic content of the input current is increased but kept within the limits imposed by the IEC standard. Two methodologies for implementing the proposed technique are discussed along the text. The first one is related to the injection of harmonic components to the duty cycle signal by means of additional branches inserted in the conventional control structure. This approach was applied to design an off-line flyback-based LED driver and also a circuit based on the Integrated Double Buck-boost converter. This first study was expanded to other topologies and a generalized analysis regarding the impact of the duty cycle modulation on off-line converters is then presented. The second methodology for implementing the ripple compensation is based on the optimization of a proportional-integral controller so that this element is designed to influence not only in the dynamic behavior of the circuit, but also in its low-frequency characteristic. Finally, the main contributions of this work are discussed and the proposals for future works are presented.

The thesis deals with the use of tribodiagnostics in predictive maintenance in corporate practice. It is generally dealt with maintenance, then tribodiagnostics in the company Škoda Auto a.s. Used offline and online diagnostic tools are described. Emphasis is placed on verifying the functionality of the newly purchased online filter unit. The experimental part is focused on detailed analysis of the above, including comparison of measurement results offline and online diagnostics. There is also an economic evaluation of savings obtained by operation the online filter unit. In conclusion, the tribodiagnostics recommendations are given for Škoda Auto a.s.