High-speed ADC is essential in radio network systems for communications. However, accuracy is an important feature for them, their precision can be affected by minor discrepancies, e.g., offset voltage of comparators, which is a primary contributor to these discrepancies. This master thesis focuses on evaluating offset calibration techniques used for high-speed comparators. To start, a literature review is performed to learn about high-speed comparators and various offset calibration techniques, which helps to understand existing problems and new ideas in offset calibration. As the next step, evaluation and implementation of the reviewed literatures are done, which involves the implementation of schematics at the transistor level, where the calibration procedure's controller is implemented in Verilog-A. Finally, an extensive set of simulations, i.e., done by the electronic design automation tool, is conducted on the designed offset calibration techniques and how they affect the general operation of high-speed ADCs.  Among the reviewed calibration techniques, two discrete adjustment methods (trans-conductance and capacitive DAC) and three voltage-controlled methods (unbalanced clocks, second differential pair, and body bias) are implemented and evaluated. The discrete methods use digital circuits, which have large variations in step sizes due to mismatches, leading to higher offsets after calibration. Monte Carlo simulations are done to show this drawback clearly better. However, using thermometer code instead of the binary-weighted would help by making the step sizes more consistent, which yields better-offset calibration results. On the other hand, the voltage-controlled methods rely on external voltages, which require more design work because of the Digital-to-Analog Converter (DAC) units. During a calibration test with various input offsets, the 'Body Bias' technique exhibited the highest precision by achieving the smallest remaining offset.