The StrongARM comparator is utilized in many analog-to-digital converters (ADCs) because of its high power efficiency and rail-to-rail outputs. The performance of the comparator directly affects the speed, power, and accuracy of an ADC. However, the StrongARM comparator performance parameters such as delay, noise, and offset measured directly from silicon prototypes are rare in literature and often consist of small sample sets. In addition, existing techniques to measure the comparator require large chip areas, making it impractical to characterize a large number of comparators to obtain stochastic parameters such as offset and noise. This work presents novel circuit techniques to measure a large number of comparators (4,000) in a compact chip area to directly obtain silicon data including delay, noise, offset, and power. The proposed techniques also relax the requirement on the test instruments to measure the small time values. Four comparators with different transistor size ratios have been designed and measured to study the performance tradeoffs. In addition, this work presents a method utilizing supercomputing resources to simulate the large design space of the StrongARM comparator to observe the performance trends. Measurements are compared to simulations showing their accuracy and, for the first time, detailed study on the performance trends with different transistor size ratios.

<p>This report briefly describes the special requirements for a computer board for use in space. In particular, component selection and ways of mitigating the soft and hard errors are discussed. Furthermore, one implementation for a low-cost, relatively high performance computer that will work in the harsh space environment is presented. The report is primarily intended for those familiar with digital design, who need an introduction to construction of space or other high-reliability hardware. </p><p>As the quality (resolution) of imagers, spectrometers and other data sources in scientific satellite payloads is increasing, there is also an increasing demand for more processing power in order to compress or in other way process the data before transmitting it on the limited bandwidth microwave downlink to Earth. Scientific instruments are usually mission specific and have rather low budget, so there is a need for a powerful computer board that can be used for a number of missions in order to keep the engineering costs down.</p>

This report briefly describes the special requirements for a computer board for use in space. In particular, component selection and ways of mitigating the soft and hard errors are discussed. Furthermore, one implementation for a low-cost, relatively high performance computer that will work in the harsh space environment is presented. The report is primarily intended for those familiar with digital design, who need an introduction to construction of space or other high-reliability hardware. As the quality (resolution) of imagers, spectrometers and other data sources in scientific satellite payloads is increasing, there is also an increasing demand for more processing power in order to compress or in other way process the data before transmitting it on the limited bandwidth microwave downlink to Earth. Scientific instruments are usually mission specific and have rather low budget, so there is a need for a powerful computer board that can be used for a number of missions in order to keep the engineering costs down.

High-speed ADC is essential in radio network systems for communications. However, accuracy is an important feature for them, their precision can be affected by minor discrepancies, e.g., offset voltage of comparators, which is a primary contributor to these discrepancies. This master thesis focuses on evaluating offset calibration techniques used for high-speed comparators. To start, a literature review is performed to learn about high-speed comparators and various offset calibration techniques, which helps to understand existing problems and new ideas in offset calibration. As the next step, evaluation and implementation of the reviewed literatures are done, which involves the implementation of schematics at the transistor level, where the calibration procedure's controller is implemented in Verilog-A. Finally, an extensive set of simulations, i.e., done by the electronic design automation tool, is conducted on the designed offset calibration techniques and how they affect the general operation of high-speed ADCs.  Among the reviewed calibration techniques, two discrete adjustment methods (trans-conductance and capacitive DAC) and three voltage-controlled methods (unbalanced clocks, second differential pair, and body bias) are implemented and evaluated. The discrete methods use digital circuits, which have large variations in step sizes due to mismatches, leading to higher offsets after calibration. Monte Carlo simulations are done to show this drawback clearly better. However, using thermometer code instead of the binary-weighted would help by making the step sizes more consistent, which yields better-offset calibration results. On the other hand, the voltage-controlled methods rely on external voltages, which require more design work because of the Digital-to-Analog Converter (DAC) units. During a calibration test with various input offsets, the 'Body Bias' technique exhibited the highest precision by achieving the smallest remaining offset.