• Refine Query
  • Source
  • Publication year
  • to
  • Language
  • 2
  • Tagged with
  • 3
  • 3
  • 3
  • 2
  • 1
  • 1
  • 1
  • 1
  • 1
  • 1
  • 1
  • 1
  • 1
  • 1
  • 1
  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Design and Measurement of StrongARM Comparators

Whitehead, Nathan Robert 29 October 2019 (has links)
The StrongARM comparator is utilized in many analog-to-digital converters (ADCs) because of its high power efficiency and rail-to-rail outputs. The performance of the comparator directly affects the speed, power, and accuracy of an ADC. However, the StrongARM comparator performance parameters such as delay, noise, and offset measured directly from silicon prototypes are rare in literature and often consist of small sample sets. In addition, existing techniques to measure the comparator require large chip areas, making it impractical to characterize a large number of comparators to obtain stochastic parameters such as offset and noise. This work presents novel circuit techniques to measure a large number of comparators (4,000) in a compact chip area to directly obtain silicon data including delay, noise, offset, and power. The proposed techniques also relax the requirement on the test instruments to measure the small time values. Four comparators with different transistor size ratios have been designed and measured to study the performance tradeoffs. In addition, this work presents a method utilizing supercomputing resources to simulate the large design space of the StrongARM comparator to observe the performance trends. Measurements are compared to simulations showing their accuracy and, for the first time, detailed study on the performance trends with different transistor size ratios.
2

Intelligent ECG Acquisition and Processing System for Improved Sudden Cardiac Arrest (SCA) Prediction

Kota, Venkata Deepa 12 1900 (has links)
The survival rate for a suddent cardiac arrest (SCA) is incredibly low, with less than one in ten surviving; most SCAs occur outside of a hospital setting. There is a need to develop an effective and efficient system that can sense, communicate and remediate potential SCA situations on a near real-time basis. This research presents a novel Zeolite-PDMS-based optically unobtrusive flexible dry electrodes for biosignal acquisition from various subjects while at rest and in motion. Two zeolite crystals (4A and 13X) are used to fabricate the electrodes. Three different sizes and two different filler concentrations are compared to identify the better performing electrode suited for electrocardiogram (ECG) data acquisition. A low-power, low-noise amplifier with chopper modulation is designed and implemented using the standard 180nm CMOS process. A commercial off-the-shelf (COTS) based wireless system is designed for transmitting ECG signals. Further, this dissertation provides a framework for Machine Learning Classification algorithms on large, open-source Arrhythmia and SCA datasets. Supervised models with features as the input data and deep learning models with raw ECG as input are compared using different methods. The machine learning tool classifies the datasets within a few minutes, saving time and effort for the physicians. The experimental results show promising progress towards advancing the development of a wireless ECG recording system combined with efficient machine learning models that can positively impact SCA outcomes.
3

A 64-channel back-gate adapted ultra-low-voltage spike-aware neural recording front-end with on-chip lossless/near-lossless compression engine and 3.3V stimulator in 22nm FDSOI

Schüffny, Franz Marcus, Zeinolabedin, Seyed Mohammad Ali, George, Richard, Guo, Liyuan, Weiße, Annika, Uhlig, Johannes, Meyer, Julian, Dixius, Andreas, Hänzsche, Stefan, Berthel, Marc, Scholze, Stefan, Höppner, Sebastian, Mayr, Christian 21 February 2024 (has links)
In neural implants and biohybrid research systems, the integration of electrode recording and stimulation front-ends with pre-processing circuitry promises a drastic increase in real-time capabilities [1,6]. In our proposed neural recording system, constant sampling with a bandwidth of 9.8kHz yields 6.73μV input-referred noise (IRN) at a power-per-channel of 0.34μW for the time-continuous ΔΣ−modulator, and 0.52μW for the digital filters and spike detectors. We introduce dynamic current/bandwidth selection at the ΔΣ and digital filter to reduce recording bandwidth at the absence of spikes (i.e. local field potentials). This is controlled by a two-level spike detection and adjusted by adaptive threshold estimation (ATE). Dynamic bandwidth selection reduces power by 53.7%, increasing the available channel count at a low heat dissipation. Adaptive back-gate voltage tuning (ABGVT) compensates for PVT variation in subthreshold circuits. This allows 1.8V input/output (IO) devices to operate at 0.4V supply voltage robustly. The proposed 64-channel neural recording system moreover includes a 16-channel adaptive compression engine (ACE) and an 8-channel on-chip current stimulator at 3.3V. The stimulator supports field-shaping approaches, promising increased selectivity in future research.

Page generated in 0.0601 seconds