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Recently, active matrix flat-panel displays are widely used in consumer electronic products. With increasing popularity of flat-panel displays, market competition becomes more intense and demands for high performance flat-panel displays are increasing. Low-temperature polysilicon (LTPS) with higher mobility, as well as drive current can integrate electric circuit, such as controllers and memory on glass substrate of display to achieve the purpose of system on panel (SOP). Thus, flat-panel displays can be more compact, while reducing reliability issues and lowering production costs. In this dissertation, we studied the nonvolatile memory for system on panel applications and reducing cost of memory by increasing the memory density or reducing the processing steps. Therefore, we proposed several modes of operation in nonvolatile memory. First, we use channel hot-electron (CHE) to inject electrons into the nitride layer that¡¦s above source or drain sides of SONOS thin film transistor (TFT). Thus, we can increase the memory density by storing two-bit state in a memory cell. In this study, the two-bit memory effect is clearly observed for devices with a shorter gate length after CHE programming; however, the two-bit memory effect is absent in devices with a longer gate length. The gate-length-dependent two-bit memory effect is related to the location of injected electrons in the nitride layer. When electrons are injected into the nitride layer above the channel, they can create an additional energy barrier in the channel thus increasing the threshold voltage of the device to perform the programming operations. However, if electrons are injected into the depletion region at the P-N junction between the drain and the channel, the energy barrier induced by electrons is not significant when exchanging the source and drain electrodes to measure the memory status, and the program effect is not as significant. When the channel length is shorten, the built-in potential between the source and the channel can be decreased, the energy barrier caused by programmed electrons can affect electrons in the channel and increase the threshold voltage. Therefore, the two-bit memory effect can be seen in devices with the shorter gate length after CHE programming. Secondly, we stored charges in the body of the thin film transistor to make the conventional thin-film transistors become a non-volatile memory. This method does not need a floating gate or a tunneling oxide in the memory cell; therefore the memory cost can be reduced. In this study, we used trap-assisted band-to-band thermionic field emission enhanced by self-heating in TFT to produce electron-hole pairs. The hole will be separated by a vertical field under the gate and be injected into the body of TFT to complete the programming operation. The erasing operation is performed by applying a lateral electric field between the source/drain to remove holes in the body of TFT. Thirdly, we proposed an edge-FN tunneling method to allow SONOS TFT possess not only a pixel switch but also a two-bit nonvolatile memory function in a display panel, thus causing the memory density to increase. In this study, we used a channel FN tunneling to program the SONOS TFT. Because the electric field in the gate-to-drain overlap region is larger than that in the channel region, it will cause a smoother electron injection into the nitride layer inside of the gate-to-drain overlap region, which also increases the gate-induced drain leakage (GIDL) current. The edge-FN tunneling method is used to erase electrons in the gate-to-drain overlap region, by doing so, the GIDL current has decreased. The memory status at the source/drain side is determined by the corresponding GIDL current of the SONOS TFT. Fourthly, we stored electrons in the nitride layer at source, channel, and drain regions of SONOS TFT to make sure that TFT possess a three-bit memory effect in a unitary cell, which also allows the memory density to increase significantly. In this study, programming and erasing operations in the source/drain region are performed by channel hot-electron injection and edge-FN tunneling method, while that in the channel region are accomplished by channel FN tunneling. The memory status in the source/drain is determined by the corresponding GIDL current, while that in the channel region by threshold voltage of the device The memory density for the device operated by proposed method can be further increased. In addition, if we store a number of N different types of electrons in those three regions mentioned above, there are N3 status can be stored in a memory cell. The memory density can beyond conventional multi-level-cell (MLC) flash memory. Two-bit memory effect per cell in a MLC flash memory can be achieved by storing four quantitative electrons in the floating gate of the memory device. If we store four quantitative electrons in the nitride layer at source, channel, and drain regions of SONOS TFT, we can obtain 64 memory states or 6-bit memory effect in a memory cell. Thus, the proposed concept is promising to storage the messages in a memory cell beyond four-bit.

abstract: In recent years, the Silicon Super-Junction (SJ) power metal-oxide semiconductor field-effect transistor (MOSFET), has garnered significant interest from spacecraft designers. This is due to their high breakdown voltage and low specific on-state resistance characteristics. Most of the previous research work on power MOSFETS for space applications concentrated on improving the radiation tolerance of low to medium voltage (~ 300V) power MOSFETs. Therefore, understanding and improving the reliability of high voltage SJMOS for the harsh space radiation environment is an important endeavor.In this work, a 600V commercially available silicon planar gate SJMOS is used to study the SJ technology’s tolerance against total ionizing dose (TID) and destructive single event effects (SEE), such as, single event burnout (SEB) and single event gate rupture (SEGR). A technology computer aided design (TCAD) software tool is used to design the SJMOS and simulate its electrical characteristics. Electrical characterization of SJMOS devices showed substantial decrease in threshold voltage and increase in leakage current due to TID. Therefore, as a solution to improve the TID tolerance, metal-nitride-oxide-semiconductor (MNOS) capacitors with different oxide/nitride thickness combinations were fabricated and irradiated using a Co-60 gamma-source. Electrical characterization showed all samples with oxide/nitride stack gate insulators exhibited significantly higher tolerance to irradiation when compared to metal-oxide-semiconductor capacitors. Heavy ion testing of the SJMOS showed the device failed due to SEB and SEGR at 10% of maximum rated bias values. In this work, a 600V SJMOS structure is designed that is tolerant to both SEB and SEGR. In a SJMOS with planar gate, reducing the neck width improves the tolerance to SEGR but significantly changes the device electrical characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P+-plug are added to the trench gate SJ power transistor to improve SEB tolerance. Using TCAD simulations, the proposed trench gate structure and the tested planar gate SJMOS are compared. The simulation results showed that the SEB and SEGR hardness in the proposed structure has improved by a factor of 10 and passes at the device’s maximum rated bias value with improved electrical performance. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2020

This thesis discusses the growth of thin-film silicon layers suitable for solar cells using liquid phase epitaxy and the behaviour of oxide LPCVD silicon nitride stacks on silicon in a high temperature ambient.¶ The work on thin film cells is focussed on the characteristics of layers grown using liquid phase epitaxy. The morphology resulting from different seeding patterns, the transfer of dislocations to the epitaxial layer and the lifetime of layers grown using oxide compared with carbonised photoresist barrier layers are discussed. The second half of this work discusses boron doping of epitaxial layers. Simultaneous layer growth and boron doping is demonstrated, and shown to produce a 35um thick layer with a back surface field approximately 3.5um thick.¶ If an oxide/nitride stack is formed in the early stages of cell processing, then characteristics of the nitride may enable increased processing flexibility and hence the realisation of novel cell structures. An oxide/nitride stack on silicon also behaves as a good anti- reflection coating. The effects of a nitride deposited using low pressure chemical vapour deposition on the underlying wafer are discussed. With a thin oxide layer between the silicon and the silicon nitride, deposition is shown not to significantly alter effective life-times.¶ Heating an oxide/nitride stack on silicon is shown to result in a large drop in effective Lifetimes. As long as at least a thin oxide is present, it is shown that a high temperature nitrogen anneal results in a reduction in surface passivation, but does not significantly affect bulk lifetime. The reduction in surface passivation is shown to be due to a loss of hydrogen from the silicon/silicon oxide interface and is characterised by an increase in Joe. Higher temperatures, thinner oxides, thinner nitrides and longer anneal times are all shown to result in high Joe values. A hydrogen loss model is introduced to explain the observations.¶ Various methods of hydrogen re-introduction and hence Joe recovery are then discussed with an emphasis on high temperature forming gas anneals. The time necessary for successful Joe recovery is shown to be primarily dependent on the nitride thickness and on the temperature of the nitrogen anneal. With a high temperature forming gas anneal, Joe recovery after nitrogen anneals at both 900 and 1000oC and with an optimised anti-reflection coating is demonstrated for chemically polished wafers.¶ Finally the effects of oxide/nitride stacks and high temperature anneals in both nitrogen and forming gas are discussed for a variety of wafers. The optimal emitter sheet resistance is shown to be independent of nitrogen anneal temperature. With textured wafers, recovery of Joe values after a high temperature nitrogen anneal is demonstrated for wafers with a thick oxide, but not for wafers with a thin oxide. This is shown to be due to a lack of surface passivation at the silicon/oxide interface.