The thesis focuses on designing and characterizing SiC 3.3 kV Diffused Metal-Oxide Semiconductor Field-Effect Transistor (DMOSFET)s with a Ron that is significantly lower than that of current commercial devices. The On-state resistance and breakdown voltage are then adjusted by adding a Super-Junction structure. Because of the pillar structure below the p-base area, the depletion will occur both vertically and horizontally and keeps the electric field distribution throughout the drift layer constant. The Super Junction Metal-Oxide Semiconductor Field-Effect Transistor (SJ MOSFET) has a good advantage compared to DMOSFETs. Due to its capacity to tolerate higher breakdown voltages and the fact that it does not require an increase in cell pitch to reach higher voltages, the Super-Junction approach is now the subject of effective research as compared to IGBTs and DMOSFETs. Silicon Carbide , a material with a wide bandgap that facilitates high temperature operation, high blocking voltage, high current flow and high switching frequency, is used to construct the device. In order to maintain a consistent electric field throughout the device, the concentration of the n and p pillars was chosen with a good charge balance between them. The outcomes of designing and simulating a DMOSFET, a Semi-SJ MOSFET, and a Full SJ MOSFET are compared in this research. The semi SJ device resulted in a Ron of 18.4 mΩcm2 and a Vb of 4.1 kV. The full SJ device reached a Ron of 12.4 mΩcm2 and a breakdown voltage of 4.2 kV. One optimized device was chosen from the semi SJ devices and used in several TCAD simulations, and the outcomes were evaluated based on the JFET width, pillar thickness, and charge imbalance between the p and n pillars. In this study, the device was also modelled for 6.5 kV and 10 kV SiC blocking voltage capabilities; the findings are also discussed. / Denna uppsats fokuserar på att utveckla och karakterisera 3.3 kV kiselkarbidbaserade DMOSFET-transistorer med betydligt lägre framspänningsfall jämfört med kommersiella halvledarkomponenter. Framspänningsfallet och spärrspänningen modifieras genom att använda en pelarliknande halvledarstruktur i drift regionen, dvs. en super-junction [SJ] struktur. På grund av pelarstrukturen under p-bas området, uppträder utarmningsområdet av laddningsbärare både vertikalt och horisontellt och ger ett konstant elektriskt fält genom drift-regionen. Super-junction transistorer har flera fördelar jämfört med komponenter i DMOSFET struktur. På grund av sin kapacitet att motstå högre spärrspänningar och genom att strukturen inte behöver en större enhetscellbredd för att nå högre spärrspänning, så är just nu super-junction strukturer i stort forskningsfokus jämfört med IGBT och DMOSFET komponenter. Kiselkarbid, ett material med ett brett bandgap, möjliggör komponenter för höga temperaturer, höga spärrspänningar, höga elektriska strömmar, samt höga växlingsfrekvenser, har använts för att bygga de undersökta komponenterna. För att generera ett konstant elektriskt fält över drift-regionen, så har dopningsnivåerna för n- och p- pelarna valts för att hålla en bra laddningsbalans mellan dem. Simuleringsresultaten av dessa komponentstrukturer, DMOSFET, halv-SJ MOSFET, och hel-SJ MOSFET är jämförda i detta projekt. Halv-SJ MOSFET transistorn resulterade i ett framspänningsfall på 18.4 mΩcm2 och når en spärrspänning av 4.1 kV. Hel-SJ MOSFET strukturen uppnår ett framspänningsfall på 12.4 mΩcm2 och med spärrspänning av 4.2 kV. En optimerad halv-SJ struktur valdes ut för att genomföra ytterligare TCAD simuleringsstudier om effekterna av JFET bredd, pelartjocklek, samt laddningsobalans mellan n- och p- pelarna. I den här studien simulerades även komponentstrukturer för 6.5 kV och 10 kV spärrspänningsklasser; även dessa resultat diskuteras i rapporten.

abstract: In recent years, the Silicon Super-Junction (SJ) power metal-oxide semiconductor field-effect transistor (MOSFET), has garnered significant interest from spacecraft designers. This is due to their high breakdown voltage and low specific on-state resistance characteristics. Most of the previous research work on power MOSFETS for space applications concentrated on improving the radiation tolerance of low to medium voltage (~ 300V) power MOSFETs. Therefore, understanding and improving the reliability of high voltage SJMOS for the harsh space radiation environment is an important endeavor.In this work, a 600V commercially available silicon planar gate SJMOS is used to study the SJ technology’s tolerance against total ionizing dose (TID) and destructive single event effects (SEE), such as, single event burnout (SEB) and single event gate rupture (SEGR). A technology computer aided design (TCAD) software tool is used to design the SJMOS and simulate its electrical characteristics. Electrical characterization of SJMOS devices showed substantial decrease in threshold voltage and increase in leakage current due to TID. Therefore, as a solution to improve the TID tolerance, metal-nitride-oxide-semiconductor (MNOS) capacitors with different oxide/nitride thickness combinations were fabricated and irradiated using a Co-60 gamma-source. Electrical characterization showed all samples with oxide/nitride stack gate insulators exhibited significantly higher tolerance to irradiation when compared to metal-oxide-semiconductor capacitors. Heavy ion testing of the SJMOS showed the device failed due to SEB and SEGR at 10% of maximum rated bias values. In this work, a 600V SJMOS structure is designed that is tolerant to both SEB and SEGR. In a SJMOS with planar gate, reducing the neck width improves the tolerance to SEGR but significantly changes the device electrical characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P+-plug are added to the trench gate SJ power transistor to improve SEB tolerance. Using TCAD simulations, the proposed trench gate structure and the tested planar gate SJMOS are compared. The simulation results showed that the SEB and SEGR hardness in the proposed structure has improved by a factor of 10 and passes at the device’s maximum rated bias value with improved electrical performance. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2020

The recent application of semiconductor materials, such as GaN, to power electronics has led to the development of a new generation of devices, which promise lower losses, higher operating frequencies and reductions in equipment size. The aim of this research is to study the capabilities of emerging GaN power devices, to understand their advantages, drawbacks, the challenges of their implementation and their potential impact on the performance of power converters. The thesis starts by presenting the development of a simple model for the switching transients of a GaN cascode device under inductive load conditions. The model enables accurate predictions to be made of the switching losses and provides an understanding of the switching process and associated energy flows within the device. The model predictions are validated through experimental measurements. The model reveals the suitability of the cascode device to soft-switching converter topologies. Two GaN cascode transistors are characterised through experimental measurement of their switching parameters (switching speed and switching loss). The study confirms the limited effect of the driver voltage and gate resistance on the turn-off switching process of a cascode device. The performance of the GaN cascode devices is compared against state-of-the-art super junction Si transistors. The results confirm the feasibility of applying the GaN cascode devices in half and full-bridge circuits. Finally, GaN cascode transistors are used to implement a 270V - 28V, 1.5kW, 1 MHz phase-shifted full-bridge isolated converter demonstrating the use of the devices in soft-switching converters. Compared with a 100 kHz silicon counterpart, the magnetic component weight is reduced by 69% whilst achieving a similar efficiency of 91%.