Magistro darbe ištirta ir iš dalies įvertinta 10 kV kabelinių linijų Šiauliuose būklė: nustatytas bendras šio tipo kabelinių linijų ilgis, kabelių tiesimo metų ir kabelių tipų santykis, movų skaičius ir jų tipai, pateikta prognozė, kokių gedimų gali kilti ateityje. / The aim of the master's paper is to investigate and evaluate the 10 kV cable line state in Šiauliai city.The LESTO Šiauliai unit has provided information about the 10 kV cable lines used in Šiauliai city: common length of this type of cable lines, cable laying year and cable types, numbers of couplings numbers and their types. The information obtained was processed using Excel and Matlab, a cable length and installation year ratio and coupling types reflective graphics were prepared.

Šiame darbe nagrinėjamos skirstomojo tinklo 0,4- 10 kV linijų gedimų problemos, remiantis mokslinės literatūros analize ir praktinio darbo patirties apibendrinimu. Nustatomi Šiaulių regiono kiekvieno rajono elektros tinklų 0,4-10 kV linijų gedimų skaičius, atjungtų vartotojų skaičius, atjungimų trukmės ir priežastys. Apskaičiuojami Šiaulių regiono kiekvieno rajono elektros tinklo patikimumo rodikliai, daugiausiai gendančios elektros linijos parengties ir priverstinės prastovos koeficientai bei veikimo ir gedimo tikimybės per 12 mėnesių. / This paper deals with the distribution network of 0.4 and 10 kV line fault problems based on the scientific literature and practical experience. The number of faults, the number of disconnections, the disconnections times and reasons of 0.4-10 kV grid lines of Šiauliai region have been investigated. Reliability indicators of electrical network of Šiauliai region have been calculated. Working and failure probabilities of the electrical network during 12 months have been calculated.

The electric power system is undergoing a paradigm change on how electric energy is generated, transmitted, and delivered. Power electronics systems which can provide medium-voltage (MV) to high-voltage (HV) output (>13.8 kV ac, > 20 kV dc) with much faster dynamic response (> 10 kHz bandwidth) or high switching-frequency will enable new electronic energy network architectures, like MVDC power delivery, underground solid-state power substation (SSPS), and high-density power electronics building block (PEBB); help drive the levelized cost of electricity (LCOE) of renewable energy on par with conventional power generation; deliver precise and clean power to loads like high-speed electric motors; push the future power system toward 100% renewable energy and energy storage supplied. In the MV to HV area, the power conversion solution is dominated by silicon devices, like SCR, IGCT, and IGBT, which are slow in nature, posing significant switching losses and bulky auxiliary components like turn-on snubbers. Devices in series are required to reach higher voltage. High-frequency HV converter in two-level or three-level bridges running 20 kHz or higher in many emerging applications, like MVDC networks with high-frequency transformers and energy storage integration is hard to be built by silicon solutions. The emerging HV wide-bandgap (WBG) power semiconductors, e.g., 10 kV SiC MOSFETs offer higher blocking capability, faster and more efficient switching performances. This makes the high-frequency power conversion technology feasible for the MV area. To build a MV high-frequency power converter with high-power density, 10 kV SiC MOSFETs in series are required to reach >10 kV operation dc voltage as the single device rating is still limited by the semiconductor process and packaging capability. However, the knowledge of dynamic voltage sharing of high-speed HV SiC devices under high dv/dt rate and effective balancing methods are not fully explored. Both the voltage imbalance and the robust device voltage balancing control are not studied clearly in the existing literature. This dissertation evaluates the voltage imbalance of series-connected 10 kV SiC MOSFETs thoroughly. The parasitic capacitors connected with device terminals are found to be a unique factor for the voltage imbalance of series-connected SiC MOSFETs, which have a significant impact on the dv/dt of different devices based on the detailed analysis. The unbalanced dv/dt and the gate signal mismatch together result in the voltage imbalance of series-connected SiC MOSFETs and a set of new voltage balancing control methods are proposed. Passive capacitor compensation and closed-loop short pulse gate signal control are proposed to solve the voltage imbalance caused by the unbalanced dv/dt. Closed-loop gate delay time control is proposed to solve the voltage imbalance caused by the gate signal mismatch. Two gate driver prototypes are designed and verified for the proposed voltage balancing control methods. As the number of devices increases, the voltage balancing methods under the device-level will be complex and risky to coordinate. Therefore, the converter-level device voltage balancing methods are desired when over three devices are in stack. Therefore, this dissertation proposes to use the 3-level (3L) neutral-point-clamped (NPC) converter structure as a converter-level approach to simplify the voltage balancing control of series-connected SiC MOSFETs. A new modulation strategy is proposed to control the loss of clamping diodes, so compact MV SiC Schottky diodes can be selected to reduce the impact of extra components on the power density. Compared to the phase-leg with direct series-connected SiC MOSFETs, the phase-leg designed with the converter-level approach achieves similar power density, easier voltage balancing control, and better efficiency, which is attractive for both two and four devices in series connection. Finally, this dissertation studies the impact of series-connected 10 kV SiC MOSFETs on MV phase-leg volume reduction with the example of multi-level flying capacitor (FC) converters. The relation between the capacitances of FCs and the device voltage is studied and a new design procedure for FCs is developed to achieve minimum FC energy and regulate the maximum device voltage. With the design procedure, the total FC volumes of a 22 kV 5-level FC converter and a 22 kV 3-level FC converter with series-connected 10 kV SiC MOSFETs are calculated and compared. Series-connected 10 kV SiC MOSFETs are found to help significantly reduce the total FC volume (> 85 %). In summary, this dissertation demonstrates that the direct series connection of 10 kV SiC MOSFETs is a reliable solution for the MV converter design, and the converter-level approach is a better voltage balancing control method. This dissertation also presents a quantitative analysis of the volume reduction enabled by the series-connected 10 kV SiC MOSFETs in MV converter phase-leg design. / Doctor of Philosophy / Emerging industrial applications require medium voltage (MV) power converters. For existing MV converter solutions with Si IGBT, complex system structures are usually required, which affects the efficiency, power density, and cost of the system. For the design of MV converter, the recent 10 kV SiC MOSFET has the promising potential to improve efficiency and power density by adopting a simpler topology and fewer conversion stages. New design challenges also emerge with the new 10 kV SiC MOSFETs and one of them is the device voltage control during the operation. This dissertation mainly focuses on the voltage balancing control of series-connected 10 SiC MOSFETs, which is an attractive solution to build the MV converter phase-leg in a simple structure. Several voltage balance control methods are proposed and compared in this dissertation, which helps justify that the series-connected SiC MOSFET is a reliable approach for the MV converter design. In addition, this dissertation also analyzes the volume reduction enabled by the series-connected SiC MOSFETs with the example of a multi-level flying capacitor converter in dc-ac applications.

The thesis focuses on designing and characterizing SiC 3.3 kV Diffused Metal-Oxide Semiconductor Field-Effect Transistor (DMOSFET)s with a Ron that is significantly lower than that of current commercial devices. The On-state resistance and breakdown voltage are then adjusted by adding a Super-Junction structure. Because of the pillar structure below the p-base area, the depletion will occur both vertically and horizontally and keeps the electric field distribution throughout the drift layer constant. The Super Junction Metal-Oxide Semiconductor Field-Effect Transistor (SJ MOSFET) has a good advantage compared to DMOSFETs. Due to its capacity to tolerate higher breakdown voltages and the fact that it does not require an increase in cell pitch to reach higher voltages, the Super-Junction approach is now the subject of effective research as compared to IGBTs and DMOSFETs. Silicon Carbide , a material with a wide bandgap that facilitates high temperature operation, high blocking voltage, high current flow and high switching frequency, is used to construct the device. In order to maintain a consistent electric field throughout the device, the concentration of the n and p pillars was chosen with a good charge balance between them. The outcomes of designing and simulating a DMOSFET, a Semi-SJ MOSFET, and a Full SJ MOSFET are compared in this research. The semi SJ device resulted in a Ron of 18.4 mΩcm2 and a Vb of 4.1 kV. The full SJ device reached a Ron of 12.4 mΩcm2 and a breakdown voltage of 4.2 kV. One optimized device was chosen from the semi SJ devices and used in several TCAD simulations, and the outcomes were evaluated based on the JFET width, pillar thickness, and charge imbalance between the p and n pillars. In this study, the device was also modelled for 6.5 kV and 10 kV SiC blocking voltage capabilities; the findings are also discussed. / Denna uppsats fokuserar på att utveckla och karakterisera 3.3 kV kiselkarbidbaserade DMOSFET-transistorer med betydligt lägre framspänningsfall jämfört med kommersiella halvledarkomponenter. Framspänningsfallet och spärrspänningen modifieras genom att använda en pelarliknande halvledarstruktur i drift regionen, dvs. en super-junction [SJ] struktur. På grund av pelarstrukturen under p-bas området, uppträder utarmningsområdet av laddningsbärare både vertikalt och horisontellt och ger ett konstant elektriskt fält genom drift-regionen. Super-junction transistorer har flera fördelar jämfört med komponenter i DMOSFET struktur. På grund av sin kapacitet att motstå högre spärrspänningar och genom att strukturen inte behöver en större enhetscellbredd för att nå högre spärrspänning, så är just nu super-junction strukturer i stort forskningsfokus jämfört med IGBT och DMOSFET komponenter. Kiselkarbid, ett material med ett brett bandgap, möjliggör komponenter för höga temperaturer, höga spärrspänningar, höga elektriska strömmar, samt höga växlingsfrekvenser, har använts för att bygga de undersökta komponenterna. För att generera ett konstant elektriskt fält över drift-regionen, så har dopningsnivåerna för n- och p- pelarna valts för att hålla en bra laddningsbalans mellan dem. Simuleringsresultaten av dessa komponentstrukturer, DMOSFET, halv-SJ MOSFET, och hel-SJ MOSFET är jämförda i detta projekt. Halv-SJ MOSFET transistorn resulterade i ett framspänningsfall på 18.4 mΩcm2 och når en spärrspänning av 4.1 kV. Hel-SJ MOSFET strukturen uppnår ett framspänningsfall på 12.4 mΩcm2 och med spärrspänning av 4.2 kV. En optimerad halv-SJ struktur valdes ut för att genomföra ytterligare TCAD simuleringsstudier om effekterna av JFET bredd, pelartjocklek, samt laddningsobalans mellan n- och p- pelarna. I den här studien simulerades även komponentstrukturer för 6.5 kV och 10 kV spärrspänningsklasser; även dessa resultat diskuteras i rapporten.

The demand for high-power converters are surging due to applications like renewable energy, motor drives and grid-interface applications. Typically, these converters’ power ranges from tens of kilowatts (kW) to several megawatts (MW). To reach such high power levels the converter voltage ratings must increase, as the current ratings cannot be reached by the available devices or because the system losses become excessive. To address this, two strategies can be utilized: multilevel topologies (e.g. Multilevel Modular Converter or Flying Capacitor Multilevel Converter) and high voltage switches. For medium voltage applications, the most commonly employed switches are the IGBT and the IGCT. Both are silicon-based technology and are limited to a rated voltage of 6.5 kV and 4.5 kV, respectively. Often, these devices switching frequency are limited to less than 1 kHz. To expand the frontiers of medium voltage converters and to demonstrate the capabilities of wide band gap devices in medium voltage, a 7-level 13.8 kV AC 22 kV DC 1.1 MW flying capacitor multilevel converter based on 10 kV SiC MOSFET with 2.5 kHz switching frequency was designed and constructed. Given the complexity of a multilevel topology, the high voltage levels, and the critical nature of the loads, a failure in a high-power converter can incur significant costs, long service downtime, and safety risks to personnel. Hence, understanding the failure modes of these converters is essential for designing protections and mitigation strategies to prevent or reduce the risks of failures. Furthermore, the adoption of 10 kV SiC MOSFET introduces additional challenges in terms of protection. Despite their well-known benefits, these devices exhibit shorter energy withstanding time compared with their silicon counterpart, and increased insulation stress resulting from the high dv/dt imposed by the fast-switching transient at higher voltages. In this context, a failure mode analysis was conducted for the converter aforementioned. The analysis examined the fault dynamics and evaluated the protections schemes at the converter level. The study identified a failure mechanism between cells, so called Cell Short- Circuit Fault (CSCF), capable of damaging the entire phase-leg. In response, a protection scheme based on TVS (Transient Voltage Suppression) diodes was designed to prevent extremely imbalanced cell voltages and failure propagation. Because of the high electric field intensity environment of the converter, an FEA (Finite Element Analyses) simulation is performed to verify and control the electric field (E-field) intensity within the protection module itself and in the converter assembly. Next, the protection module insulation design was successfully verified in a Partial Discharge (PD) experiment. In sequence, an experimental verification utilizing an equivalent circuit based on the fault model demonstrated the efficacy of the protection module. Waveforms extracted while the converter was operating showing the protection module acting during a fault are presented and analyzed. Finally, the influence of the protection module in the switching of the 10 kV SiC MOSFET was evaluated via a double pulse test (DPT), revealing negligible effects on the converter performance. / Center of Power Electronics Systems (CPES) Department of Energy (DoE) / Master of Science / Due to governmental policies and market opportunities renewable energy (e.g. solar and wind energy) is increase its share in the electricity generation in the US and around the world. This scenario poses challenges regarding the stability of the grid and variation in the generation along the day. One of the alternatives to alleviate the problem is to use highpower converters that provides a interface between grid and manufacturing plants. This type of converter have bidirectional capabilities and can store the energy generated by solar farms during the day and return it to the grid at night for example. Moreover, it can provide grid support capabilities in terms of variation of frequency and voltage. To expand on the grid interface converters application concept, a medium voltage power converter in 22 kV DC and 13.8 kV AC is designed utilizing novel techniques and the latest technologies in semiconductors, 10 kV SiC MOSFETs. The benefits of this design are a small form factor, high efficiency, immunity to electromagnetic interference and power quality. This work presents a failure mode analysis of the power converter aforementioned, the analysis examined the fault dynamics and an evaluation of the protections schemes at the converter level. The failure analysis revealed the need of a protection scheme extremely imbalanced cell voltages and failure propagation. Hence, a protection module based on TVS (Transient Voltage Suppression) diodes was successfully designed and tested. Due to the high voltages present in this equipment, an FEA (Finite Element Analyses) simulation is performed to verify and control the electric field (E-field) intensity within the protection module itself and in the converter assembly. Experimental results are provided for insulation design integrity (partial discharge test), for the efficacy of the protection module against the fault, and for the impact of the protection module on the operation performance.

Detta arbete har utförts hos Varberg Energi AB och syftat till att presentera olika koncept som alternativ till konventionella 130 kV luftisolerade fördelningsstationer. Arbetet är tänkt att kunna vara en del i en uppdragsbeskrivning för en kommande ombyggnation. De alternativ som står tillbuds bygger ofta på att någon eller flera komponenter innehåller svavelhexafluorid, SF6, vilken har en stor negativ påverkan på växthuseffekten om den släpps ut i atmosfären. De alternativ av komponenter, exempelvis brytare, som inte innehåller SF6 är få och väsentligt mycket dyrare. Dock är fortfarande konceptlösningar som använder sig av luft som isolationsmedium till komponenter som inte är brytare, frånskiljare eller dylikt de billigaste.  Alternativen som framkommit i denna rapport och studerats närmare är ABB:s Urban-koncept, GIS med SF6 och Siemens Blue GIS med renad luft och vakuumbrytare. Fokus har varit lösningarnas beskaffenhet gällande säkerhet för tredje man, enkelhet i underhåll, klimatpåverkan och tillförlitlighet. Önskvärt är en helhetslösning där underhåll eller reparationer kan utföras i de olika facken i 130 kV-stationen utan att det påverkar driften och orsakar ett avbrott. Att finna en lösning som inte kräver SF6-gas i någon del av fördelningsstationen ger många lättnader i regelverk, mindre övervakning och kostnader förknippade med denna. En balansgång behöver göras mellan ekonomiska intressen, miljöpåverkan, inspektionsintervall, felavhjälpning och eventuella framtida miljökrav för högspänningsanläggningar. Det förstärkta sabotageskyddet som en byggnad ger har varit en klar fördel som lyfts fram hos de besökta anläggningarna. Vid val av konceptlösning kan storleken hos och kompetensen inom den egna organisationen vara en faktor att ta hänsyn till. Även utformning och val av lösning för tidigare och framtida stationer kan behöva tas hänsyn till.

<div>Power semiconductor devices play an important role in many areas, including household</div><div>appliances, electric vehicles, high speed trains, electric power stations, and renewable energy</div><div>conversion. In the modern era, silicon based devices have dominated the semiconductor</div><div>market, including power electronics, because of their low cost and high performance. The</div><div>applications of devices rated 600 V - 6.5 kV are still dominated by silicon devices, but they</div><div>are nearly reaching fundamental material limits. New wide band gap materials such as silicon</div><div>carbide (SiC) offer significant performance improvements due to superior material properties</div><div>for such applications in and beyond this voltage range. 4H-SiC is a strong candidate</div><div>among other wide band gap materials because of its high critical electric field, high thermal</div><div>conductivity, compatibility with silicon processing techniques, and the availability of high</div><div>quality conductive substrates.</div><div>Vertical DMOSFETs and insulated gate bipolar transistors (IGBT) are key devices for</div><div>high voltage applications. High blocking voltages require thick drift regions with very light</div><div>doping, leading to specific on-resistance (R_ON,SP ) that increases with the square of blocking</div><div>voltage (V_BR). In theory, superjunction drift regions could provide a solution because of a</div><div>linear dependence of R_ON,SP on V_BR when charge balance between the pillars is achieved</div><div>through extremely tight process control. In this thesis, we have concluded that superjunction</div><div>devices inevitably have at least some level of charge imbalance which leads to a quadratic</div><div>relationship between V_BR and R_ON,SP . We then proposed an optimization methodology to</div><div>achieve improved performance in the presence of this inevitable imbalance.</div><div>On the other hand, an IGBT combines the benefits of a conductivity modulated drift</div><div>region for significantly reduced specific on-resistance with the voltage controlled input of a</div><div>MOSFET. Silicon carbide n-channel IGBTs would have lower conduction losses than equivalent</div><div>DMOSFETs beyond 6.5 kV, but traditionally have not been feasible below 15 kV. This</div><div>is due to the fact that the n+ substrate must be removed to access the p+ collector of the</div><div>IGBT, and devices below 15 kV have drift layers too thin to be mechanically self-supporting.</div><div>In this thesis, we have demonstrated the world’s first functional 10 kV class n-IGBT with</div><div>a waffle substrate through simulation, process development, fabrication and characterization.</div><div><div>The waffle substrate would provide the required mechanical support for this class of devices.</div><div>The fabricated IGBT has exhibited a differential R_ON,SP of 160 mohm</div><div>.cm², less than half of</div><div>what would be expected without conductivity modulation. An extensive fabrication process</div><div>development for integrating a waffle substrate into an active IGBT structure is described</div><div>in this thesis. This process enables an entirely new class of moderate voltage SiC IGBTs,</div><div>opening up new applications for SiC power devices.</div></div>