No description available.

No description available.

No description available.

No description available.

No description available.

by Yiu Sau Yan Vincent. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1996. / Includes bibliographical references (leaves 86-88). / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Related Works --- p.3 / Chapter 2.1 --- Tightly-coupled Parallel Systems --- p.5 / Chapter 2.2 --- Loosely-coupled Parallel Systems --- p.6 / Chapter 3 --- Communication Protocol --- p.11 / Chapter 3.1 --- Terminology --- p.12 / Chapter 3.2 --- CUP Model --- p.14 / Chapter 3.3 --- Message Format --- p.15 / Chapter 3.4 --- Message Header --- p.16 / Chapter 3.5 --- Message Content - Control Message --- p.17 / Chapter 3.6 --- Message Transfer Functions --- p.18 / Chapter 3.7 --- Application Development --- p.22 / Chapter 4 --- Multiple Computer Infrastructure --- p.28 / Chapter 4.1 --- Application Supper --- p.32 / Chapter 4.1.1 --- Send and Receive --- p.34 / Chapter 4.1.2 --- Multicast --- p.35 / Chapter 4.1.3 --- Barrier Synchronization --- p.36 / Chapter 4.1.4 --- Start and Delete Process --- p.37 / Chapter 4.2 --- Local Message Routing --- p.39 / Chapter 4.2.1 --- Berkeley Socket --- p.40 / Chapter 4.2.2 --- System V Message Queue --- p.45 / Chapter 4.2.3 --- Shared Memory Queue SMQ --- p.47 / Chapter 4.3 --- Network Message Routing --- p.49 / Chapter 4.3.1 --- Ethernet & TCP Socket --- p.51 / Chapter 4.3.2 --- SCSI Link --- p.52 / Chapter 5 --- System Supporting Facilities --- p.54 / Chapter 5.1 --- Kernel Message Support --- p.54 / Chapter 5.2 --- SCSI Hardware & Device Driver --- p.60 / Chapter 5.2.1 --- SCSI Bus Operations --- p.61 / Chapter 5.2.2 --- Device Driver Internals --- p.65 / Chapter 6 --- Performance --- p.73 / Chapter 7 --- Conclusion --- p.83 / Chapter 7.1 --- Summary of Our Research --- p.83 / Chapter 7.2 --- Future Researches --- p.84

The contents of this thesis are concerned with the implementation of parallel algorithms for solving partial differential equations (POEs) by the Alternative Group EXplicit (AGE) method and an investigation into the numerical inversion of the Laplace transform on the Balance 8000 MIMO system. Parallel computer architectures are introduced with different types of existing parallel computers including the Data-Flow computer and VLSI technology which are described from both the hardware and implementation points of view. The main characteristics of the Sequent parallel computer system at Loughborough University is presented, and performance indicators, i.e., the speed-up and efficiency factors are defined for the measurement of parallelism in the system. Basic ideas of programming such computers are also outlined.....

With the availability of fast microprocessors and small-scale multiprocessors, internode communication has become an increasingly important factor that limits the performance of parallel computers. Essentially, message-passing parallel computers require extremely short communication latency such that message transmissions have minimal impact on the overall computation time. This thesis concentrates on issues regarding hardware communication latency in single-hop reconfigurable networks, and software communication latency regardless of the type of network. The first contribution of this thesis is the design and evaluation of two different categories of prediction techniques for message-passing systems. This thesis utilizes the communications locality property of message-passing parallel applications to devise a number of heuristics that can be used to predict the target of subsequent communication requests, and to predict the next consumable message at the receiving ends of communications. Specifically, I propose two sets of predictors: Cycle-based predictors, which are purely dynamic predictors, and Tag-based predictors, which are static/dynamic predictors. The performance of the proposed predictors, specially Better-cycle2 and Tag-bettercycle2, are very well on the application benchmarks studied in this thesis. The proposed predictors could be easily implemented on the network interface due to their simple algorithms and low memory requirements. As the second contribution of this thesis, I show that majority of reconfiguration delays in single-hop reconfigurable networks can be hidden by using one of the proposed high hit ratio predictors. The proposed predictors can be used in establishing a communication pathway between a source and a destination in such networks before this pathway is to be used. This thesis' third contribution is the analysis of a broadcasting algorithm that utilizes latency hiding and reconfiguration in the network to speed the broadcasting operation. The analysis brings up closed formulations that yields the termination time of the algorithms. The thesis' fourth contribution is a new total exchange algorithm in single-hop reconfigurable networks. I conjecture that this algorithm ensures a better termination time than what can be achieved by either of the direct, and standard exchange algorithms. The fifth contribution of this thesis is the use and evaluation of the proposed predictors to predict the next consumable message at the receiving ends of communications. This thesis contributes by claiming that these message predictors can be efficiently used to drain the network and cache the incoming messages even if the corresponding receive calls have not been posted yet. This way, there is no need to copy the early arriving messages into a temporary buffer. The performance of the proposed predictors, Single-cycle, Tag-cycle2 and Tag-bettercycle2, on the parallel applications are quite promising and suggest that prediction has the potential to eliminate most of the remaining message copies. / Graduate

No description available.

No description available.