Trying to do two things at once decreases performance of one or both tasks in many cases compared to the situation when one performs each task by itself. The present thesis deals with the question why and in which cases these dual-task costs emerge and moreover, whether there are cases in which people are able to process two cognitive tasks at the same time without costs. In four experiments the influence of stimulus-response (S-R) compatibility, S-R modality pairings, interindividual differences, and practice on parallel processing ability of two tasks are examined. Results show that parallel processing is possible. Nevertheless, dual-task costs emerge when: the personal processing strategy is serial, the two tasks have not been practiced together, S-R compatibility of both tasks is low (e.g. when a left target has to be responded with a right key press and in the other task an auditorily presented “A” has to be responded by saying “B”), and modality pairings of both tasks are Non Standard (i.e., visual-spatial stimuli are responded vocally whereas auditory-verbal stimuli are responded manually). Results are explained with respect to executive-based (S-R compatibility) and content-based crosstalk (S-R modality pairings) between tasks. Finally, an alternative information processing account with respect to the central stage of response selection (i.e., the translation of the stimulus to the response) is presented. / Versucht man zwei Aufgaben zur gleichen Zeit zu erledigen, so verschlechtert sich die Leistung einer oder beider Aufgabe(n) im Vergleich zur Situation, in der man beide Aufgaben einzeln erledigt. Die vorliegende Dissertation beschäftigt sich mit der Frage, warum und unter welchen Umständen diese Doppelaufgabenkosten entstehen. Darüber hinaus geht sie der Frage nach, ob es Aufgabenkombinationen gibt, für die parallele Verarbeitung ohne Kosten gezeigt werden kann. In vier Experimenten wurde der Einfluss von Stimulus-Reaktion (S-R) Kompatibilität, S-R Modalitätspaarungen, interindividueller Unterschiede und Training auf das Parallelverarbeitungspotential zweier Aufgaben untersucht. Die Ergebnisse zeigen, dass parallele Verarbeitung generell möglich ist. Dennoch entstehen Doppelaufgabenkosten, wenn die persönliche Verarbeitungsstrategie seriell ist, die beiden Aufgaben nicht genügend zusammen trainiert wurden, die S-R Kompatibilität beider Aufgaben gering ist (z.B. wenn ein linker Zielreiz mit einem Druck auf die rechten Taste beantwortet und in der anderen Aufgabe ein auditiv präsentiertes „A“ mit der Aussprache eines „Bs“ beantwortet werden muss) und die Modalitätspaarungen beider Aufgaben Nicht-Standard sind (d.h. visuell-räumliche Stimuli mit vokalen und auditiv-verbale Stimuli mit manuellen Reaktionen beantwortet werden müssen). Die gewonnenen Ergebnisse werden durch „Crosstalk“ der exekutiven Signale (S-R Kompatibilität) und durch inhaltsbasierten „Crosstalk“ (S-R Modalitätspaarungen) erklärt. Weiterhin wird ein alternatives Modell der Informationsverarbeitung mit Hinblick auf die zentrale Phase der Antwortauswahl (d.h. die Phase in der die Stimulusinformation in eine Antwort übersetzt wird) vorgestellt.

User-programmable, integrated circuits (ICs) e.g. Field Programmable Gate Arrays (FPGAs) are increasingly popular for embedded, high-performance data exploitation. They combine the parallelization capability and processing power of application specific integrated circuits (ASICs) with the exibility, scalability and adaptability of software-based processing solutions. FPGAs provide powerful processing resources due to an optimal adaptation to the target application and a well-balanced ratio of performance, efficiency and parallelization. One drawback of FPGA-based data exploitation is the limited memory capacity of reconfigurable integrated circuits. Large-scale Digital Signal Processor (DSP) FPGAs provide approximately 4MB on-board random access memory (RAM) which is not sufficient to buffer the broadband sensor and result data. Hence, additional external memory is connected to the FPGA to increase on-board storage capacities. External memory devices like double data rate three synchronous dynamic random access memories (DDR3-SDRAM) provide very fast and wide bandwidth interfaces that represent a bottleneck when used in highly parallelized processing architectures. Independent processing modules are demanding concurrent read and write access. Within the master thesis, a concept for the integration of an external DDR3- SDRAM into an FPGA-based parallelized processing architecture is developed and implemented. The solution realizes time division multiple access (TDMA) to the external memory and virtual, low-latency memory extension to the on-board buffer capabilities. The integration of the external RAM does not change the way how on-board buffers are used (control, data-fow).

User-programmable, integrated circuits (ICs) e.g. Field Programmable Gate Arrays (FPGAs) are increasingly popular for embedded, high-performance data exploitation. They combine the parallelization capability and processing power of application specific integrated circuits (ASICs) with the exibility, scalability and adaptability of software-based processing solutions. FPGAs provide powerful processing resources due to an optimal adaptation to the target application and a well-balanced ratio of performance, efficiency and parallelization. One drawback of FPGA-based data exploitation is the limited memory capacity of reconfigurable integrated circuits. Large-scale Digital Signal Processor (DSP) FPGAs provide approximately 4MB on-board random access memory (RAM) which is not sufficient to buffer the broadband sensor and result data. Hence, additional external memory is connected to the FPGA to increase on-board storage capacities. External memory devices like double data rate three synchronous dynamic random access memories (DDR3-SDRAM) provide very fast and wide bandwidth interfaces that represent a bottleneck when used in highly parallelized processing architectures. Independent processing modules are demanding concurrent read and write access. Within the master thesis, a concept for the integration of an external DDR3- SDRAM into an FPGA-based parallelized processing architecture is developed and implemented. The solution realizes time division multiple access (TDMA) to the external memory and virtual, low-latency memory extension to the on-board buffer capabilities. The integration of the external RAM does not change the way how on-board buffers are used (control, data-fow).