This paper discusses three case studies on the realization of spurious prepositions and argues that they illustrate a general interaction of convergence requirements of the morphological component with an economy condition that enforces faithfulness between the lexical items present in the numeration and the lexical items present in the PF output.

The aim is to illustrate the opinion former Torsten Tegnér’s view of sport, culture and society, the nature of the influence he exerted primarily through his own professional magazine, Idrottsbladet, a liberal-conservative sports journalist’s attitude in confrontation with other social attitudes and some questions of principle and debates that were topical during the period within Swedish sport. Five thematic chapters demonstrate how Tegnér reacted to developments within sport that were due to social changes. Above all, the research demonstrates that the values he wished to communicate principally dealt with a healthy soul in a healthy body for the benefit and happiness of both the individual and society. Secondly, he wished to convey the culture of the middle classes. In the background, the concept of freedom was a constant overarching ideology. His reactions to the developments can be seen in the light of his passion for sport as beneficial, his family’s combination of liberalism and respect for traditions and their expectations of him, his understanding of democracy and a touch of post-Romanticism. His passion for freedom led to his political involvement against Nazism and Communism in particular. Tegnér’s means of influencing are viewed from a power perspective. As a well-qualified intellectual, by means of a significant symbolic capital, with Idrottsbladet’s position and as ‘a one-man civic educator’, he was one of those who, in the opinion of the philosopher Antonio Gramsci, were particularly important in a social power game. It is particularly interesting that his circle of readers seems to have overwhelmingly consisted of working-class youngsters.

The number of wireless communication applications increase steadily, leading to the competition for currently allocated frequency bands. Pressure on authorities around the world to permit communications in higher and wider frequency ranges to achieve higher wireless capacity than those existed in the past has resulted in several new specifications. The federal communication commission (FCC) in USA has unleashed the band 3.1-10.6 GHz for ultra-wideband radio (UWB) communications. The release has triggered a worldwide interest for UWB. Other regulatory instances throughout the world have issued use of UWB techniques as well. Capacity issues in form of data rate and latency have always been a bottleneck for broadened wireless-communication usages. New communication systems like UWB require larger bandwidth than what is normally utilized with traditional antenna techniques. The interest for compact consumer electronics is growing in the meantime, creating a demand on efficient and low profile antennas which can be integrated on a printed circuit board. In this thesis, some methods to extend the bandwidth and other antenna parameters associated with wideband usages are studied. Furthermore, methods on how to enhance the performance when one antenna-element is not enough are studied as well. The principle of antenna parallelism is demonstrated using both microstrip patch antennas and inverted-F antennas. Several techniques to combine the antennas in parallel have been evaluated. Firstly, a solution using power-splitters to form sub-arrays that covers one 500-MHz multi-band orthogonal frequency division multiplexing (OFDM) UWB is shown in Paper I. It is then proposed that the sub-bands are selected with a switching network. A more convenient method is to use the later developed frequency multiplexing technique as described in Paper V and VIII. Using the frequency multiplexing technique, selective connection of any number of antennas to a common junction is possible. The characteristic impedance is chosen freely, typically using a 50-Ω feed-line. Secondly, in Paper VIII a frequency-triplexed inverted-F antenna system is investigated to cover the Mode 1 multi-band UWB bandwidth 3.1-4.8 GHz. The antenna system is composed of three inverted-F antennas and a frequency triplexer including three 5th order bandpass filters. In Paper VI a printed circuit board integrated-triplexer for multi-band UWB radio is presented. The triplexer utilizes a microstrip network and three combined broadside- and edge-coupled filters. The triplexer is fully integrated in a four metal-layer printed circuit board with the minimum requirement on process tolerances. Furthermore, the system is built completely with distributed microstrips, i.e., no discrete components. Using the proposed solution an equal performance between the sub-bands is obtained. Finally suitable monopoles and dipoles are discussed and evaluated for UWB. In Paper X circular monopole and dipole antennas for UWB utilizing the flex-rigid concept are proposed. The flex-rigid concept combines flexible polyimide materials with the regular printed circuit board material. The antennas are placed entirely on the flexible part while the antenna ground plane and the dipole antenna balun are placed in the rigid part.

The Multi-Level Computing Architecture (MLCA) is a multiprocessor system-on-chip architecture designed for multimedia applications. It provides a programming model that simplifies the process of writing parallel applications by eliminating the need for explicit synchronization. However, developers must still invest effort to design applications that fully exploit the MLCA’s multiprocessing capabilities. We present a set of compiler techniques to streamline the process of developing applications for the MLCA. We present an algorithm to automatically partition a sequential application into tasks that can be executed in parallel. We also present code generation algorithms to translate annotated, sequential C code to the MLCA’s programming model. We provide an experimental evaluation of these techniques, performed with a prototype compiler based upon the open-source ORC compiler and integrated with the MLCA Optimizing Compiler. This evaluation shows that the performance of automatically generated code compares favourably to that of manually written code.

Graphics Processing Units (GPUs) have become a competitive accelerator for non-graphics applications, mainly driven by the improvements in GPU programmability. Although the Compute Unified Device Architecture (CUDA) is a simple C-like interface for programming NVIDIA GPUs, porting applications to CUDA remains a challenge to average programmers. In particular, CUDA places on the programmer the burden of packaging GPU code in separate functions, of explicitly managing data transfer between the host and GPU memories, and of manually optimizing the utilization of the GPU memory. We have designed hiCUDA, a high-level directive-based language for CUDA programming. It allows programmers to perform these tedious tasks in a simpler manner, and directly to the sequential code. We have also prototyped a compiler that translates a hiCUDA program to a CUDA program and can handle real-world applications. Experiments using seven standard CUDA benchmarks show that the simplicity hiCUDA provides comes at no expense to performance.

Graphics Processing Units (GPUs) have become a competitive accelerator for non-graphics applications, mainly driven by the improvements in GPU programmability. Although the Compute Unified Device Architecture (CUDA) is a simple C-like interface for programming NVIDIA GPUs, porting applications to CUDA remains a challenge to average programmers. In particular, CUDA places on the programmer the burden of packaging GPU code in separate functions, of explicitly managing data transfer between the host and GPU memories, and of manually optimizing the utilization of the GPU memory. We have designed hiCUDA, a high-level directive-based language for CUDA programming. It allows programmers to perform these tedious tasks in a simpler manner, and directly to the sequential code. We have also prototyped a compiler that translates a hiCUDA program to a CUDA program and can handle real-world applications. Experiments using seven standard CUDA benchmarks show that the simplicity hiCUDA provides comes at no expense to performance.

The Multi-Level Computing Architecture (MLCA) is a multiprocessor system-on-chip architecture designed for multimedia applications. It provides a programming model that simplifies the process of writing parallel applications by eliminating the need for explicit synchronization. However, developers must still invest effort to design applications that fully exploit the MLCA’s multiprocessing capabilities. We present a set of compiler techniques to streamline the process of developing applications for the MLCA. We present an algorithm to automatically partition a sequential application into tasks that can be executed in parallel. We also present code generation algorithms to translate annotated, sequential C code to the MLCA’s programming model. We provide an experimental evaluation of these techniques, performed with a prototype compiler based upon the open-source ORC compiler and integrated with the MLCA Optimizing Compiler. This evaluation shows that the performance of automatically generated code compares favourably to that of manually written code.

El objetivo de este Trabajo Final es comparar el efecto de la distribución de trabajo estática y dinámica sobre arquitecturas de cluster heterogéneo, analizando al mismo tiempo el speedup paralelo teórico y el obtenido experimentalmente para un determinado tipo de problema. En particular, se ha elegido una aplicación clásica (Parallel N-Queens) con un algoritmo de solución paralela en la que predomina el procesamiento sobre el tamaño de los datos, de modo de profundizar en los aspectos del balance de carga (estático o dinámico) sin una distorsión de los resultados producida por aspectos relacionados al uso de la memoria y/o al tamaño de los mensajes a comunicar. Para la experimentación se ha utilizado una combinación de 4 clusters interconectados, donde las máquinas dentro de cada grupo poseen procesadores homogéneos, pero diferentes entre clusters. De este modo el conjunto puede verse como un cluster heterogéneo de 43 procesadores. El problema se ha resuelto utilizando el paradigma master/worker donde el procesamiento se descompone en tareas irregulares que atentan contra el balance de carga entre los procesadores. Por esta razón se han analizado tres estrategias de distribución de trabajo calculando en cada caso el desbalance de carga y el rendimiento obtenido, comparando los resultados para determinar la que tiene mejor comportamiento, y finalmente estudiar la escalabilidad para esa solución. La solución paralela pura (sin tener en cuenta la distribución del trabajo) para el tipo de problemas donde Tp>>Tc, en particular el de N-Reinas requiere mínima comunicación entre máquinas, lo que hace esencial la elección de la distribución de datos entre los procesadores, para alcanzar un speedup cercano al óptimo (es decir un buen rendimiento).

There has recently been a resurgence in interest in techniques for effective programming of multi-core computers. Most programmers find general-purpose concurrent programming to be extremely difficult. This difficulty severely limits the number of applications that currently benefit from multi-core computers. There already exist many concurrent solutions for the class of regular applications, which include various algorithms for linear algebra. For the class of irregular applications, which operate on dynamic and pointer- and graph-based structures, efficient concurrent solutions have so far remained elusive. Dataflow analysis applications, which are often found in compilers and program analysis tools, have received particularly little attention with regard to execution on multi-core machines. Operating on the theory that the Actor model, which structures computations as systems of asynchronously-communicating entities, is a more appropriate method for representing irregular algorithms than the shared-memory model, this work presents a concurrent Actor-based formulation of the IFDS, or Interprocedural Finite Distributive Subset, dataflow analysis algorithm. The implementation of this algorithm is done using the Scala language and its Actors library. This algorithm achieves significant speedup on multi-core machines without using any optimistic execution. This work contributes to Actor research by showing how the Actor model can be practically applied to a dataflow analysis problem. This work contributes to static analysis research by showing how a dataflow analysis algorithm can effectively make use of multi-core machines, allowing the possibility of faster and more precise analyses.

As emerging portable multimedia applications demand more and more computational throughput with limited energy consumption, the need for high-efficiency, high-throughput embedded processing is becoming an important challenge in computer architecture. In this regard, this dissertation addresses application-, architecture-, and technology-level issues in existing processing systems to provide efficient processing of multimedia in many, or ideally all, of its form. In particular, this dissertation explores color imaging in multimedia while focusing on two architectural enhancements for memory- and performance-hungry embedded applications: (1) a pixel-truncation technique and (2) a color-aware instruction set (CAX) for embedded multimedia systems. The pixel-truncation technique differs from previous techniques (e.g., 4:2:2 and 4:2:0 subsampling) used in image and video compression applications (e.g., JPEG and MPEG) in that it reduces the information content in individual pixel word sizes rather than in each dimension. Thus, this technique drastically reduces the bandwidth and memory required to transport and store color images without perceivable distortion in color. At the same time, it maintains the pixel storage format of color image processing in which each pixel computation is performed simultaneously on 3-D YCbCr components, which are widely used in the image and video processing community. CAX supports parallel operations on two-packed 16-bit (6:5:5) YCbCr data in a 32-bit datapath processor, providing greater concurrency and efficiency for processing color image sequences. This dissertation presents the impact of CAX on processing performance and on both area and energy efficiency for color imaging applications in three major processor architectures: dynamically scheduled (superscalar), statically scheduled (very long instruction word, VLIW), and embedded single instruction multiple data (SIMD) array processors. Unlike typical multimedia extensions, CAX obtains substantial performance and code density improvements through direct support for color data processing rather than depending solely on generic subword parallelism. In addition, the ability to reduce data format size reduces system cost. The reduction in data bandwidth also simplifies system design. In summary, CAX, coupled with the pixel-truncation technique, provides an efficient mechanism that meets the computational requirements and cost goals for future embedded multimedia products.