The InGaP Heterojunction Bipolor Transistors (HBTs) become known as the dominant technology in handset power amplifiers. Modern application requirements and size limitations have driven industry leaders towards the co-integration of enhance/depletion mode pHEMT and HBT. The combination of BiFET gives an additional degree of freedom in the design of advanced power amplifiers combine switch. This dissertation provides an overview of the various techniques. Critical processes included gate photolithography and Polyimide planarize process are discussed in detail. The 0.5-£gm multiple gate fingers fabricated on the controllable small un-gated region of a high-topology wafer was overcome by using a bi-layer photolithography process. The fabricated of polyimide was used as the dielectric interlayer to reduce the interconnect crossover parasitic capacitance and planarize the second metal process for metal shunt application. The metal shunt structures provide greater functionality and design flexibility under shrinking. Finally, presents the combine the best features of InGaP HBT-pHEMT integration technology. The HBT and E/D-pHEMT electrical performances (DC, small signal, noise, and power) are presented. The results indicate that this technology offers great potential and degrees of freedom to design power amplifiers, high-integrated RF transceivers, and opportunities for the development of novel RFIC circuits.

The development of monolithic microwave integrated circuits (MMICs) has enabled the expansion of multiple circuit elements on a single piece of semiconductor, enclosed in a package with connecting leads. Attributable to the widespread use of wireless circuits and sub-systems, MMICs meet stringent demands for smaller chip area, low loss and low cost. These require highly integrated MMICs with compact features. This thesis provides valuable insight into the design of compact multifunctional MMICs using three-dimensional (3-D) multilayer technology. The proposed technology offers compact, hence low-cost solutions, where all active and passive components are fabricated vertically on the same substrate and no expensive via hole or backside processing is required. The substrate used in this work contains pre-fabricated 0.5 µm pseudomorphic High Electron Mobility Transistor (pHEMT) GaAs active devices. The performances of the uncommitted and committed pHEMTs are compared in terms of their DC, small-signal and large-signal RF measurements and modelling results. Committed pHEMT refers to the pHEMT that is connected to multilayer circuit, whereas uncommitted pHEMT is not. The effect of integrating committed pHEMTs with multilayer passive components is studied and the suitability of the multilayer fabrication processing is assessed. Using this technology, two pHEMT Schottky diodes with 120 µm and 200 µm gate widths are designed, fabricated and extensively characterised by I-V, C-V and S-parameter measurements. The information gained from the measurements is then used to extract all unknown equivalent circuit model parameters using high-frequency on-wafer microwave probing. The measured results showed good agreement with the modelled ones over the frequency range up to 40 GHz. Preliminary demonstrations of the use of these pHEMT Schottky diodes in microwave limiter and detector circuit applications are also discussed, showing promising results. Finally, the implementation of 3-D multilayer technology is shown for the first time in single-pole single-throw (SPST) and single-pole double-throw (SPDT) switches design by utilising the pre-fabricated pHEMTs. The design and analysis of the switches are demonstrated first through simulation using TriQuint's Own Model - Level 3 (TOM3). Three optimised SPST and SPDT pHEMT switching circuits which can address applications ranging from L to X bands are successfully fabricated and tested. The performance of the pHEMT switches is comparable to those of the current state-of-the-art, while simultaneously offering compact circuits with the advantages of integration with other MMIC components. All works reported in this thesis should facilitate foundry design engineers towards further development of 3-D multilayer technology.

InP-based InAlAs/InGaAs pseudomorphic High Electron Mobility Transistors (pHEMTs) have shown outstanding performance; this makes them prominent in high frequency mm-wave and submillimeter-wave applications. However, conventional InGaAs/InAlAs pHEMTs have major drawbacks, i.e., very low breakdown voltage and high gate leakage current. These disadvantages degrade device performance, especially in Monolithic Microwave Integrated Circuit (MMIC) low noise amplifiers (LNAs). The optimisation of InAlAs/InGaAs epilayer structures through advanced bandgap engineering offers a key solution to the problem. Concurrently, device modelling plays a vital role in the design and analysis of pHEMT devices and circuit performance. In this research, two-dimensional (2D) physical modelling of 1 m and sub-micro metre gate length strained channel InAlAs/InGaAs/InP pHEMTs has been developed, in ATLAS Silvaco. All modelled devices were optimised and validated by experimental devices, which were fabricated at the University of Manchester. An underlying device physics insight is gained, i.e., the effect of changes to the device's physical structure, theoretical concepts and its general operation, and a reliable pHEMT model is obtained. The kink anomalies in the I-V characteristics were reproduced. The 2D simulation results demonstrate an outstanding agreement with measured DC and RF characteristics. The aim of developing linear and non-linear models for sub-micro metre transistors and their implementation in MMIC LNA design is achieved with the 0.25 m In0.7Ga0.3As/In0.52Al0.48As/InP pHEMT. An accurate method for the extraction of empirical models for the fabricated active devices has been developed, and optimised using the Advance Design System (ADS) software. The results demonstrate excellent agreement between experimental and modelled DC and RF data. Precise models for MMIC passive devices are also obtained, and incorporated in the proposed design for a single- and double-stage MMIC LNAs at C- and X-band frequencies. The single-stage LNA is designed to achieve a maximum gain ranging from 9 to 13 dB over the band of operation, while the gain is increased to between 20 dB and 26 dB for the double-stage LNA designs. A noise figure of less than 1.2 dB and 2 dB is expected, for the C- and X-band LNAs respectively, while retaining stability across all frequency bands. Although the RF performance of pHEMT is being vigorously pushed towards the terahertz (THz) region, novel devices such as the Resonant Tunnelling Diode (RTD) are needed to support future ultra-high-speed, high-frequency applications. Hence, the study of physical modelling is extended to quantum modelling of an advanced In0.8Ga0.2As/AlAs RTD device. The aim is to effectively model both large-size and submicron RTDs, using Silvaco's ATLAS software to reproduce the peak current density, peak-to-valley-current ratio (PVCR), and negative differential resistance (NDR) voltage range. The physical modelling for the RTD devices is optimised to achieve an excellent match with the fabricated RTD devices; variations in the spacer thickness, barrier thickness, quantum well thickness and doping concentration are included.

Hall Effect integrated circuits are used in a wide range of applications to measure the strength and/or direction of magnetic fields. These sensors play an increasingly significant role in the fields of automation, medical treatment and detection thanks largely to the enormous development of information technologies and electronic industries. Commercial Hall Effect ICs available in the market are all based on silicon technology. These ICs have the advantages of low cost and compatibility with CMOS technology, but suffer from poor sensitivity and detectability, high power consumption and low operating frequency bandwidths. The objective of this work was to develop and fabricate the first fully monolithic GaAs-InGaAs-AlGaAs 2-Dimensional Electron Gas (2DEG) Hall Effect integrated circuits whose performance enhances pre-existing technologies. To fulfil this objective, initially 2 µm gate length pHEMTs and 60/20 µm (L/W) Greek cross Hall Effect sensors were fabricated on optimised GaAs-In.18Ga.82As-Al.35Ga.65As 2DEG structures (XMBE303) suitable for both sensor and integrated circuit designs. The pseudomorphic high electron mobility transistors (pHEMTs) produced state-of-the-art output conductance, providing high intrinsic gain of 405, current cut-off frequency of 4.8 GHz and a low negative threshold voltage of -0.4 V which assisted in designing single supply ICs with high sensitivity and wide dynamic range. These pHEMTs were then accurately modelled for use in the design and simulation of integrated circuits. The corresponding Hall sensor showed a current sensitivity of 0.4 mV/mA.mT and a maximum magnetic DC offset of 0.35 mT at 1 V. DC digital (unipolar) and DC linear Hall Effect integrated circuits were then designed, simulated, fabricated and fully characterised. The DC linear Hall Effect IC provided an overall sensitivity of 8 mV/mT and a power consumption as low as 6.35 mW which, in comparison with commercial Si DC linear Hall ICs, is at least a factor of 2 more power efficient. The DC digital (unipolar) Hall Effect IC demonstrated a switching sensitivity of 6 mT which was at least ~50% more sensitive compared to existing commercial unipolar Si Hall ICs. In addition, a novel low-power GaAs-InGaAs-AlGaAs 2DEG AC linear Hall Effect integrated circuit with unprecedented sensitivity and wide dynamic range was designed, simulated, fabricated and characterised. This IC provided a sensitivity of 533 nV/nT, minimum field detectability of 177 nT (in a 10 Hz bandwidth) at frequencies from 500 Hz up to 200 kHz, consuming only 10.4 mW of power from a single 5 V of supply. In comparison to commercial Si linear Hall ICs, this IC provides an order of magnitude larger sensitivity, a factor of 4 higher detectability, 20 times wider bandwidth and over 20% lower power consumption (10.4 mW vs. 12.5 mW). These represent the first reported monolithic integrated circuits using a CMOS-like technology but in GaAs 2DEG technology and are extremely promising as complements, if not alternatives, to CMOS Si devices in high performance applications (such as high temperatures operations (>150 °C) and radiation hardened environment in the nuclear industry).

This thesis offers the design and improvement of a 2 GHz to 20 GHz low noise amplifier (LNA) utilizing pHEMT technology. The pHEMT technology allows the LNA to generate a boosted signal at a lower noise figure (NF) while consuming less power and achieving smooth overall gain. The design achieves an overall gain (S21) of ≥ 10 dB with an NF ≤ 2 dB while consuming ≤ 30 mA of power while using commercial off-the-shelf (COTS) components.

Yes / This work develops a novel dynamic load modulation Power Amplifier (PA) circuity that can provide an optimum compromise between linearity and efficiency while covering multiple cellular frequency bands. Exploiting monolithic microwave integrated circuits (MMIC) technology, a fully integrated 1W Doherty PA architecture is proposed based on 0.1 µm AlGaAs/InGaAs Depletion- Mode (D-Mode) technology provided by the WIN Semiconductors foundry. The proposed wideband DPA incorporates the harmonic tuning Class-J mode of operation, which aims to engineer the voltage waveform via second harmonic capacitive load termination. Moreover, the applied post-matching technique not only reduces the impedance transformation ratio of the conventional DPA, but also restores its proper load modulation. The simulation results indicate that the monolithic drive load modulation PA at 4 V operation voltage delivers 44% PAE at the maximum output power of 30 dBm at the 1 dB compression point, and 34% power-added efficiency (PAE) at 6 dB power back-off (PBO). A power gain flatness of around 14 ± 0.5 dB was achieved over the frequency band of 23 GHz to 27 GHz. The compact MMIC load modulation technique developed for the 5G mobile handset occupies the die area of 3.2. / This research was funded by the European Regional Development Fund (FEDER), through COMPETE 2020, POR ALGARVE 2020, Fundação para a Ciência e a Tecnologia (FCT) under i-Five Project (POCI-01-0145-FEDER-030500). This work is also part of the POSITION-II project funded by the ECSEL joint Undertaking under grant number Ecsel-345 7831132-Postitio-II-2017-IA. This work is supported by FCT/MCTES through national funds and when applicable co-funded EU funds under the project UIDB/50008/2020-UIDP/50008/2020. The authors would like to thank the WIN Semiconductors foundry for providing the MMIC GaAs pHEMT PDKs and technical support. This work is supported by the Project TEC2017-88242-C3-2-R- Spanish Ministerio de Ciencia, Innovación e Universidades and EU-FEDER funding.

In a radio frequency (RF) system, the front-end of a radio receiver consists of an active antenna arrangement with a conducting mode antenna along with an active circuit. This arrangement helps avoid losses and SNR degradation due to the use of a coaxial cable. The active circuit is essentially an impedance matching network and a low noise amplification (LNA) stage. The input impedance of the antenna is always different from the source impedance required to be presented at the LNA input for maximum power gain and this gives rise to undesired reflections at the antenna-LNA junction. This necessitates a matching network that provides the impedance matching between the antenna and the LNA at a central frequency (CF). From the Friis formula it is seen that the total noise figure (NF) of the system is dependent on the noise figure and gain of the first stage. So, by having an LNA that provides a high gain (typically >15 dB) which inserts minimum possible noise (desirably < 1 dB), the overall noise figure of the system can be maintained low. The LNA amplifies the signal to a suitable power level that will enable the subsequent demodulation and decoding stages to efficiently recover the original signal. The antenna and the LNA can be matched with each other in two possible ways. The first approach is the traditional method followed in RF engineering where in both the antenna and LNA are matched to 50 W terminations and connected to each other. In this classical method, the antenna and LNA are matched to 50 W at the CF and does not take into account the matching at other frequencies in the operation range. The second approach employs a co-design method to match the antenna and LNA without a matching network or with minimum possible components for matching. This is accomplished by varying one or more parameters of either the antenna or LNA to control the impedances and ultimately achieve a matching over a substantial range of frequencies instead at the CF alone. The co-design method is shown to provide higher gain and a lower NF with reduced number of components, cost and size as compared to the classical method. The thesis work presented here is a study, design and manufacturing of an antenna-LNA module for a wide frequency range of 1.7 GHz – 2.7 GHz to explore the gain and NF improvements in the co-design approach. Planar micro strip patch antennas and GaAs E-pHEMT transistor based LNA’s are designed and the matching and co-design are simulated to test the gain and NF improvements. Furthermore, fully functional prototypes are developed with Roger R04360 substrate and the results from simulations and actual measurements are compared and discussed.

A 5-bit MMIC serial to parallel converter has been designed in Gallium Arsenide. It is intended to be used together with a 5-bit True Time Delay (TTD) circuit, but it can easily be expanded into an arbitrary number of bits. The circuit has been designed with a logic style called DCFL and a 0.20 mm process (ED02AH) from OMMIC has been used to fabricate the circuit. The chip size of this 5-bit MMIC serial to parallel converter is 2.0x0.8 mm (including pads) and close to two hundred transistors are used. Due to the complexity of the transistor models the complete serial to parallel converter has not been fully simulated. However, the smaller building blocks like inverter, latch, etc. have been simulated successfully. These blocks were assembled into the complete circuit.

Modern phased array radars require large numbers of electronically controlled phase shifters to steer their beams to the desired direction. The amount of beam steering error depends on the phase resolution of the phase shifters as well as the performance of other parts of the antenna system. The size of the phase shifter in such systems is most of the time needed to be small, which necessitates the MMIC implementation. In the context of this thesis, an X band 7 bit MMIC phase shifter of 2.8125 degree phase resolution, including its layout, is designed using the design kit of OMMIC&reg / Foundry. All bits of the phase shifter are designed to have low return loss so as to minimize the performance egradation due to loading effects upon cascading. Also some structures studied using the design kit of WIN&reg / Foundry are presented. Both designs were performed using ADS&reg / . For the optimum cascading of 7 bits, a MATLAB code was written and used.

<p>A 5-bit MMIC serial to parallel converter has been designed in Gallium Arsenide. It is intended to be used together with a 5-bit True Time Delay (TTD) circuit, but it can easily be expanded into an arbitrary number of bits. The circuit has been designed with a logic style called DCFL and a 0.20 mm process (ED02AH) from OMMIC has been used to fabricate the circuit. The chip size of this 5-bit MMIC serial to parallel converter is 2.0x0.8 mm (including pads) and close to two hundred transistors are used. Due to the complexity of the transistor models the complete serial to parallel converter has not been fully simulated. However, the smaller building blocks like inverter, latch, etc. have been simulated successfully. These blocks were assembled into the complete circuit.</p>