Over the past two decades, power consumption has increased exponentially worldwide, posing new challenges to power grids to meet the load requirements. With this growing power demand, the need for efficient high-density medium-voltage (MV) power converters has increased to support flexible power distribution grids. The modular multilevel converters (MMC) became the most typical MV power converters in applications from 2010. This topology has many advantages, such as voltage scalability, excellent output performance, and low voltage ratings for switching devices. However, without the excellent reliability of the MMC, applications cannot reap these benefits. The MMC topology comprises several series-connected submodules (typically a half-bridge or a full-bridge inverter). As a result of increased switching devices, the converter becomes vulnerable since a single device fault can disrupt the whole converter operation. Therefore, fault-tolerant strategies to replace faulty SM with a redundant SM are developed using additional bypass switches. Conventionally TRIACs and vacuum switches are employed as bypass switches that operate in the range of 2-10 microseconds. Despite having performance advantages, MMCs are still not fully employed in aerospace and naval industries due to their enormous size. Many Power Electronics Building Blocks (PEBB) are proposed, with size optimization, as submodules for modular converters. The PEBB1000, a 1000 V- PEBB proposed by Dr. Jun Wang, achieved a significant size reduction of 80% with a novel switching cycle control (SCC) scheme. This novel control scheme requires high switching frequency and high di/dt-currents for MMC operation. Due to di/dt-rate limitations, TRIAC-based switch cannot perform bypass operation. Therefore, research work has been conducted on bypass switches for PEBB1000 using wide-bandgap SiC devices. This thesis presents the design of a SiC MOSFET-based bypass switch for PEBB1000 in MMC application. A detailed fault case analysis is presented to show the feasibility of the bypass operation for 90% PEBB-level faults. Significant variations in PEBB1000 bypass requirements are observed through SCC-based MMC simulations. Accordingly, a 1700 V, 100 A bypass switch has been designed using the anti-series topology of MOSFETs. Various specifications, such as 142 nanoseconds operation time, 500 nanoseconds bypass commutation time, and 277A transient current conduction capability, are validated through practical tests. Results prove that SiC-MOSFETs work better than TRIACs in high di/dt-current conduction and operation times. For future work, false-triggering endurance has to be analyzed for 1000 V switching voltage. / Master of Science / When a building is on fire, the safety of people inside depends on the timely arrival of the fire rescue departments. Similarly, for an electrical fault, the safety of electrical systems depends on fast and secure fault protection devices. This thesis presents work on one such fault-protection device used in the power distribution grid: solid-state bypass switch. Distribution grids supply power majorly to households and industries at the city or state level. They employ medium-voltage (MV) converters to step down the voltages to meet the distribution requirements. In MV converters, several low-voltage modules are connected in series to achieve the high-voltage power conversion. When a fault occurs at one of the low-voltage modules in MV converters, power flow gets disrupted due to a series connection like a chain. Therefore, bypass switches are connected in parallel to low-voltage modules for an alternate power flow path. Conventionally used bypass switches have 2-10 microseconds operation time. Recent advancements in semiconductor devices, SiC MOSFETs, allow operation times less than one microsecond. Therefore, research work has been conducted on bypass switches using SiC MOSFETs. Finally, the SiC-MOSFET based bypass switch is built and tested according to converter requirements. Results proved that the designed switch operates in 142 nanoseconds, ten times faster than a conventional switch.

The basic Power Electronics Building Block (PEBB) configurations are identified and conceptual PEBB modules are constructed and tested. Using the INCA (Inductance Calculator) parasitic extraction and the Saber circuit simulation software, the microscopic relationships between the parasitics of the packaging layout and their circuit electrical effects are cross-examined. The PEBB module with advanced packaging techniques is characterized in comparison with the wire-bond module. The soft-switching techniques are evaluated for PEBB applications. The Zero-Current-Transition (ZCT) is proved better because the parasitics in the power current flow path are absorbed into the resonant soft-switching operation. This makes the PEBBs insensitive to system integration. Based on the building block concept, the discrete and large signal average models are developed for simulation, design, and analysis of large-scale PEBB-based systems. New average models are developed for half-bridge PEBB module and Space Vector Modulation (SVM). These models keep the exact information of the discontinuous SVM and the common mode component of the three-phase system. They can be used to construct the computer models of a power electronics system the same as the modularized hardware and perform time domain simulations with very fast speed. Further more, even though the system is modeled based on modularized concept on the ABC coordinates, it can be used to perform small signal analysis on the DQ coordinates as well. Based on the developed models, the system-level interactions in integrated systems are investigated. Three interaction scenarios are presented: (1) the zero-sequence circulation current in paralleled three-phase rectifiers caused by the interleaved discontinuous SVM, (2) the load and source interactions caused by unbalanced load and small signal impedance overlap, and (3) the combined common mode noise caused by both front-end PWM rectifiers and load inverters. The interaction phenomena and mitigation methods are demonstrated through hardware testbed system. The concept of dc bus conditioning is proposed. The bus conditioner is a bi-directional dc/dc converter programmed as a current controlled current source, which shunts the large signal ac current, which otherwise goes to the dc bus, into an isolated energy storage component. In addition to alleviate the source and load interactions, it increases the load impedance/decreases the bus impedance and provides more stability margins to the distribution system. The dc bus conditioner concept and its functions are demonstrated through system simulation and preliminary hardware experiment. / Ph. D.

Power electronics building blocks (PEBBs) are standardized building blocks used to integrate power electronics systems. The PEBB approach can achieve low cost, high redundancy, high reliability, high flexibility and easy maintenance for large-scale power electronics systems. This thesis presents the implementation of a 100kW PEBB-based soft-switched bus regulator for an 800V DC distributed power system. The zero current transition (ZCT) soft-switching technique is used to improve the performance of the bus regulator by minimizing switching loss and improving overall efficiency. PEBB modules and a digital control building block are the subsystems of the DC bus regulator. This thesis addresses the design issues at subsystem and system levels. These include: operational principles and design of ZCT PEBB modules; design and implementation of the digital control block, based on DSP and EPLD; and modeling and control design of the DC bus regulator. There are several considerations when using the ZCT soft-switching technique in three-phase applications: the timing of the auxiliary switch gate signals must be arranged differently; there are low-frequency harmonics caused by the pulse width limits; and there is high thermal stress on the resonant capacitors. These issues are resolved by utilizing the sensed phase current information and the design freedom in the PWM modulator. A PWM modulation technique is proposed that can considerably reduce the switching events and further remove the associated loss while keeping THD low. Reduced switching events alleviate the thermal issue of the resonant capacitors. The same modulation technique can avoid the low-frequency harmonics caused by the pulse width limits and double the sampling frequency. The phase current information is used to deal with the control timing issue of the auxiliary switches and to control the three-phase soft-switching operation in order to achieve better efficiency. Additionally, the phase current information is used to implement dead time compensation to reduce THD. The soft-switched DC bus regulator has been tested up to a 100kW power level with 20kHz switching frequency. Experimental results demonstrate that high performance of the DC bus regulator is accomplished in terms of wide control bandwidth, low THD, unity power factor, high efficiency and high power density. / Master of Science

Power electronics applications in high power are normally large, expensive, spatially distributed systems. These systems are typically complex and have multiple functions. Due to these properties, the control algorithm and its implementation are challenging, and a different approach is needed to avoid customized solutions to every application while still having reliable sensor measurements and converter communication and control. This thesis proposes a synchronous digital control architecture that allows for the communication and control of devices via a fiber optic communication ring using digital technology. The proposed control architecture is a multidisciplinary approach consisting of concepts from several areas of electrical engineering. A review of the state of the art is presented in Chapter 2 in the areas of power electronics, fieldbus control networks, and digital design. A universal controller is proposed as a solution to the hardware independent control of these converters. Chapter 3 discusses how the controller was specified, designed, implemented, and tested. The power level specific hardware is implemented in modules referred to as hardware managers. A design for a hardware manager was previously implemented and tested. Based on these results and experiences, an improved hardware manager is specified in Chapter 4. A fault tolerant communication protocol is specified in Chapter 5. This protocol is an improvement on a previous version of the protocol, adding benefits of improved synchronization, multimaster support, fault tolerant structure with support for hot-swapping, live insertion and removals, a variable ring structure, and a new network based clock concept for greater flexibility and control. Chapter 6 provides a system demonstration, verifying the components work in configurations involving combinations of controllers and hardware managers to form applications. Chapter 7 is the conclusion. VHDL code is included for the controller, the hardware manager, and the protocol. Schematics and manufacturing specifications are included for the controller. / Master of Science