Les conditionneurs alternatifs – continu à absorption sinusoïdale (PFC) pour les applications critiques se distinguent par un haut niveau de performances tel que les THD réduits, un haut rendement et une bonne fiabilité. Leur importance est d’autant plus nécessaire qu’une continuité de service des alimentations est requise même en présence d’une défaillance interne de composant. Deux types de structures associées à leur commande sont réalisés à cet effet, les structures à redondance parallèle et les structure à redondance en série. Elles consistent respectivement en l’ajout d’un bras d’interrupteur dans le cas de la redondance parallèle, qui est une option plus compliquée et en une suppression d’une cellule de commutation dans le deuxième cas. L’étude présentée ici, consiste en premier lieu en une exploration et une évaluation de nouvelles familles de topologies multi-niveaux, caractérisée par un partitionnement cellulaire en série. Ces nouvelles topologies, ainsi que leurs variantes, comportent au moins une redondance structurelle avec des cellules mono-transistor à défaut de commande non critique et symétriques à point-milieu. Elles sont donc génériques pour la mise en parallèle et l’extension en triphasé. Cependant, elles sont pour la plupart peu compétitives à cause des composants qui sont souvent surdimensionnés et donc plus onéreuses, en comparaison avec la structure PFC Double-Boost 5 Niveaux à composants standards 600 V (brevetée par l’INPT – LAPLACE –CNRS en 2008) que nous étudions. Cette dernière constitue le meilleur compromis entre un bon rendement et une maîtrise des contraintes en mode dégradé. Sur le plan théorique nous montrons que le seul calcul de fiabilité basé uniquement sur un critère de premier défaut est inadapté pour décrire ce type de topologie. La prise en compte de la tolérance de panne est nécessaire et permet d'évaluer la fiabilité globale sur une panne effective (i.e. au second défaut). L'adaptation de modèles théoriques de fiabilité à taux de défaillance constant mais prenant en compte, au niveau de leurs paramètres, le report de contrainte en tension et l'augmentation de température qui résulte d'un premier défaut, permet de chiffrer en valeur relative, le gain obtenu sur un temps court. Ce résultat est compatible avec les systèmes embarqués et la maintenance conditionnelle. Un prototype monophasé de PFC double-boost 5 niveaux à commande entièrement numérique et à MLI optimisée reconfigurable en temps réelle a été réalisé afin de valider l’étude. Il permet une adaptation automatique de la topologie de 5 à 4 puis 3 niveaux par exemple. Ce prototype a également servi de test d'endurance aux transistors CoolMos et diodes SiC volontairement détruits dans des conditions d'énergie maîtrisée et reproductibles. D’autres campagnes d'endurance en modes dégradés ont été réalisées en laboratoire sur plusieurs centaines d’heures en utilisant ce même prototype. Nous nous sommes axés sur la détection de défauts internes et le diagnostic (localisation) rapide, d'une part par la surveillance directe et le seuillage des tensions internes (tensions flottantes) et d'autre part, par la détection d’harmoniques (amplitude et phase) en temps réel. Ces deux techniques ont été intégrées numériquement et évaluées sur le prototype, en particulier la seconde qui ne requiert qu'un seul capteur. Enfin, nous proposons une nouvelle variante PFC expérimentée en fin de mémoire, utilisant deux fois moins de transistors et de drivers pour les mêmes performances fréquentielles au prix d'un rendement et d'une répartition des pertes légèrement moins favorable que la structure brevetée. / This work is an exploration and an evaluation of new variants of multi-level AC/DC topologies (PFC) considering their global reliability and availability: electrical safety with an internal failure and post-failure operation. They are based on a non-differential AC and centre tap connection that led to symmetrical arrangement cells in series. These topologies permit an intrinsic active redundancy between cells in a same group and a segregation capability between the two symmetrical groups of cells. More again, they are modular and they can be paralleled and derived to any number of levels. Only single low-voltage (600V) transistor pear cell is used avoiding the short-circuit risk due to an unwanted control signal. Comparisons, taking into account losses, distribution losses, rating and stresses (overvoltage and over-temperature) during the post-operation are presented. Results highlight the proposed 5-level Double-Boost Flying Capacitor topology. This one was patented at the beginning of thesis, as a solution with the best compromise. On the theoretical side, we show that the reliability calculation based only on a "first fault occurrence" criterion is inadequate to really describe this type of topology. The inclusion of fault tolerance capability is needed to evaluate the overall reliability law (i.e. including a second failure). The adaptation of theoretical models with constant failure rate including overvoltage and over-temperature dependencies exhibit an increasing of the reliability over a short time. This property is an advantage for embedded systems with monitoring condition. Local detection and rapid diagnosis of an internal failure were also examined in this work. Two methods are proposed firstly, by a direct flying caps monitoring and secondly, by a realtime and digital synchronous demodulation of the input sampled voltage at the switching frequency (magnitude and phase). Both techniques have been integrated on FPGA and DSP frame and evaluated on a AC230V-7kW DC800V – 31kHz lab. set-up. We put forward the interest of the second method which only uses one input voltage sensor. Finally, we propose in this dissertation a new generic X-level PFC Vienna using, in 5-level version, half transistors and drivers for identical input frequency and levels. At the cost of a slight increase of losses and density losses, this topology appears very attractive for the future. A preliminary lab. set-up and test were also realized and presented at the end of the thesis.

This study aims to design a Shunt Semi-Active Power Factor Correction Circuits , which can be applied to high power circuit by low switching frequency. The designed circuit can avoid power loss working with high switching frequency when using the method of active power factor correction .The experimental configuration based on DSP is applied to a compressor of air conditioner with varied load. The simulation check the developed circuit using Ispice . Both of the experimental and simulation results have guaranteed the derived configuration reach the expected goals.

A single-stage high-power-factor electronic ballast with class E inverter is proposed for driving the fluorescent lamp. The circuit configuration is obtained from the integration of a buck-boost converter for power-factor- correction (PFC) and a class E resonant inverter for ballasting. The integrated ballast circuit requires only one active power switch and simple control. Operating the buck-boost converter in discontinuous conduction mode (DCM) at a fixed frequency, the electronic ballast can achieve nearly unity power factor. With pulse-width-modulation (PWM), the electronic ballast can provide an appropriate filament current for preheating, a high voltage for ignition, and then a desired lamp current for steady-state operation. An additional control circuit is included to eliminate the glow current during preheating stage. The operation of the ballast-lamp circuit is analyzed by fundamental approximation. Computer simulations are made and design equations are derived on basis of the power-dependent resistance model of the fluorescent lamp. With carefully designed circuit parameters, the active power switch can be switched on at zero current to reduce the switching losses leading to a higher efficiency. An experimental circuit designed for a PL-27W compact fluorescent lamp is built and tested to verify the computer simulations and analytical predictions. Experimental results show that satisfactory performances can be obtained on the proposed electronic ballast.

With the rapid evolving IT technologies, today, the power factor correction (PFC) design is facing many challenges, such as power scalability, high entire-load-range efficiency, and high power density. Power scalability is a very desirable and cost-effective approach in the PFC design in order to keep up with servers' growing power requirements. Higher power density can eventually reduce the converter cost and allows for accommodating more equipment in the existing infrastructures. Driven strongly by economic and environmental concerns, high entire-load-range efficiency is more and more required by various organizations and programs, such as the U.S. Energy Star, Climate Savers, and German Blue Angel. Today, the existing boost PFC is reaching its limitations to meet these challenges simultaneously. Using the cutting-edge semiconductor devices, further efficiency improvement at light load is still needed. There are limited approaches available for increasing the power density due to the large EMI filter and inductor size. Interleaved multi-channel boost PFC is a promising candidate to meet those challenges, but the interleaved boost converter is a less explored area. On the other hand, the multi-channel interleaved buck converter for the VR application has been intensively studied and thoroughly explored. One basic approach of this study is trying to extend the existing knowledge and techniques obtained from multiphase buck converters to the multi-channel interleaved boost converters since there are similarities existed between the multi-phase buck and the multi-channel boost converters. The existing studies about the interleaving impact on the EMI filter design are based on the time domain ripple cancellation effect. This approach is good enough for most of the filter designs. However, unlike the conventional filter designs, the EMI filter design is a specification related process. Both the EMI standard and the EMI measurement are based on the frequency domain spectrum. Limited by the existing analysis approaches, it is difficult to provide a clear picture about how exactly the multi-channel interleaving will impact the EMI filter design. The interleaving impact on the Common Mode (CM) noise also has not been studied in any existing literatures for the same reason. In this study, the frequency domain analysis method was adopted. With the double Fourier integral transformation, a closed-form expression of all the harmonics of the noise sources can be obtained. With all the detailed phase relationship of the switching frequency harmonics and all the side band harmonics, the multi-channel interleaving impact on both the differential mode (DM) and CM filter design can be clearly understood and summarized. According to the design curves provided, the EMI filter size can be effectively reduced by properly choosing the interleaving channel number and the switching frequency. The multi-channel interleaving impact on the output capacitor current ripple is also studied and summarized in this dissertation. It should be pointed out that interleaving only reduces the total input and output current ripples; the inductor current in each channel still has large ripple if small inductance is used. Similar to the multi-phase buck converter, coupling inductors result in different equivalent inductances for input current ripple and inductor current ripple for boost converters. Keeping the inductor current ripple magnitude the same, inverse coupling inductors between the interleaved channels can reduce the inductor size. However, the DM filter size is increased due to larger input current. Based on the investigation on the total magnetic component weight, inverse coupling inductor can reduce the total magnetic component weight. The reduction is more pronounced for lower switching frequency design when the inductor size is dominating among the total magnetic components. Based on the harmonic cancellation, and with all the detailed phase relationship of the switching frequency harmonics and all the side band harmonics, a novel phase angle control method is proposed to maximize the reduction of the EMI filter. For example, in a 2-channel interleaved PFC, just by changing the interleaving scheme to 90 degree phase shift, 39% total volume reduction of the EMI filter can be achieved. The proposed phase angle controlled multi-channel PFC is experimentally demonstrated and verified on a digital controlled 4-channel PFC. The phase angle control method proposed in the multi-channel boost converter can be applied back to the multi-phase buck converter as well. The harmonic cancellation principle will be the same as the multi-channel boost converter. The same benefits can be obtained when the requirement is defined in the frequency domain, e.g. the EMI Standard. The interleaved multi-channel configuration makes it possible to implement the phase-shedding to improve the PFC light load efficiency. By decreasing the number of active channels according to the load, the PFC light load efficiency can be optimized. However, shedding phases can reduce the ripple cancellation effect as well, which will result in the EMI noise increase and losing the benefit on the EMI filter. By applying the proposed phase-shedding with phase angle control strategy, the phase shedding impact on the EMI filter design can be minimized. The light load efficiency can be improved without compromising the EMI filter size. Then, adaptive frequency controlled PFC is proposed to further improve the PFC light load efficiency. The proposed light load efficiency improvement strategies are combined and implemented on the platform of the digital controlled 4-channel PFC. The benefit of improving the light load efficiency is experimentally verified. The EMI performance is also evaluated with the EMI measurement results obtained from the PFC prototype. Following the same approach explored, the benefits of interleaved boost converter can be further extended other applications, such as the boost converter in the Hybrid Electric Vehicles (HEV) and photovoltaic (PV) system. / Ph. D.

The boost power factor correction (PFC) circuit is a common circuit in power electronics. Through years of experience, many designers have optimized the design of these circuits for particular applications. In this study, a new design procedure is presented that guarantees optimal results for any application. The algorithm used incorporates the principles of evolution in order to find the best design. This new design technique requires a rethinking of the traditional design process. Electrical models have been developed specifically for use with the optimization tool. One of the main focuses of this work is the implementation and verification of computationally efficient thermal and electro-magnetic interference (EMI) models for the boost PFC circuit. The EMI model presented can accurately predict noise levels into the 100's of kilohertz range. The thermal models presented provide very fast predictions and they have been adjusted to account for different thermal flows within the layout. This tuning procedure results in thermal predictions within 10% of actual measurement data. In order to further reduce the amount of analysis that the optimization tool must perform, some of the converter design has been performed using traditional methods. This part of the design is discussed in detail. Additionally, a per unit analysis of EMI and thermal levels is introduced. This new analysis method allows EMI and thermal levels to be compared on the same scale thus highlighting the tradeoffs between the both behaviors. / Master of Science

Ce travail vise une exploration et une évaluation de nouvelles variantes de topologies multiniveaux AC/DC non réversibles (PFC) du point de vue de leur sûreté de fonctionnement : recherche d'une grande sécurité électrique sur destruction interne et maintien d'une continuité de fonctionnement. Elles sont caractérisées par une connexion AC non différentielle, un partitionnement cellulaire en série et symétrique autour d'un point milieu. Cette organisation permet d'exploiter la redondance active série entre les cellules d'un même groupe et l'effet de ségrégation topologique qui apparaît entre les deux groupes de cellules. Les structures étudiées sont modulaires et peuvent être parallélisées et étendues à un nombre quelconque de phases. Elles ne possèdent que des cellules mono-transistors basse-tension (Si et SiC 600V max) performantes et intrinsèquement tolérantes aux imperfections de la commande et aux parasites donc naturellement sécurisées. Les comparaisons prenant en compte les pertes, la répartition des pertes, le dimensionnement et le report de contraintes sur défaut interne mettent en avant la structure PFC Double- Boost Flying Cap. à 5 Niveaux, brevetée en début de thèse, comme une solution ayant le meilleur compromis. Sur le plan théorique nous montrons que le seul calcul de la fiabilité basé uniquement sur un critère d'occurrence au premier défaut est inadapté pour décrire ce type de topologie. La prise en compte de la tolérance de panne est nécessaire et permet d'évaluer la fiabilité globalement sur une panne effective (i.e. au second défaut). L'adaptation de modèles théoriques de fiabilité à taux de défaillance constant mais prenant en compte, au niveau de leurs paramètres, le report de contrainte en tension et l'augmentation de température qui résulte d'un premier défaut, permet de chiffrer par intégration et en valeur relative, le gain obtenu sur un temps court. Ce résultat est compatible avec les systèmes embarqués et la maintenance conditionnelle. Un prototype monophasé à 5 niveaux, à commande entièrement numérique et à MLI optimisée reconfigurable en temps réel a été réalisé afin de valider l'étude. Il permet une adaptation automatique de la topologie de 5 à 4 puis à 3 niveaux par exemple. Ce prototype a également servi de banc de test d'endurance du mode de défaillance sur claquage - avalanche de transistors CoolMos™ et diodes SiC, volontairement détruits individuellement dans des conditions d'énergie maîtrisée et reproductibles, afin de prouver expérimentalement le maintien du service sur plusieurs centaines d'heures au prix d'un derating de 30% maximum en puissance seulement. La détection et le diagnostic rapide de défauts internes ont également été traités dans ce travail. D'une part, par la surveillance directe et le seuillage des tensions internes (tensions flottantes) et d'autre part, par une détection harmonique de la fréquence de base (amplitude et phase) en temps réel. Ces deux techniques ont été intégrées numériquement et évaluées sur le prototype, en particulier la seconde qui ne requiert qu'un seul capteur. VI Enfin, nous proposons dans ce travail une nouvelle variante PFC Vienna multicellulaire expérimentée en fin de mémoire, utilisant deux fois moins de transistors et de drivers pour les mêmes performances fréquentielles au prix d'un rendement et d'une répartition des pertes légèrement moins favorables que la structure brevetée.

Power electronics building blocks (PEBBs) are standardized building blocks used to integrate power electronics systems. The PEBB approach can achieve low cost, high redundancy, high reliability, high flexibility and easy maintenance for large-scale power electronics systems. This thesis presents the implementation of a 100kW PEBB-based soft-switched bus regulator for an 800V DC distributed power system. The zero current transition (ZCT) soft-switching technique is used to improve the performance of the bus regulator by minimizing switching loss and improving overall efficiency. PEBB modules and a digital control building block are the subsystems of the DC bus regulator. This thesis addresses the design issues at subsystem and system levels. These include: operational principles and design of ZCT PEBB modules; design and implementation of the digital control block, based on DSP and EPLD; and modeling and control design of the DC bus regulator. There are several considerations when using the ZCT soft-switching technique in three-phase applications: the timing of the auxiliary switch gate signals must be arranged differently; there are low-frequency harmonics caused by the pulse width limits; and there is high thermal stress on the resonant capacitors. These issues are resolved by utilizing the sensed phase current information and the design freedom in the PWM modulator. A PWM modulation technique is proposed that can considerably reduce the switching events and further remove the associated loss while keeping THD low. Reduced switching events alleviate the thermal issue of the resonant capacitors. The same modulation technique can avoid the low-frequency harmonics caused by the pulse width limits and double the sampling frequency. The phase current information is used to deal with the control timing issue of the auxiliary switches and to control the three-phase soft-switching operation in order to achieve better efficiency. Additionally, the phase current information is used to implement dead time compensation to reduce THD. The soft-switched DC bus regulator has been tested up to a 100kW power level with 20kHz switching frequency. Experimental results demonstrate that high performance of the DC bus regulator is accomplished in terms of wide control bandwidth, low THD, unity power factor, high efficiency and high power density. / Master of Science

In this work, a modeling approach is delineated and described in detail; predominantly done in the time domain from low frequency, DC, to high frequencies, 100 MHz. Commercially available computer aided design tools will be used to determine the propagation path in a given structure. Next, an integrated transmission-line filter — fabricated using planar processing technologies — is modeled to accurately predict the EMI characteristics of the system. A method was derived to model the filter's performance in the time-domain while accurately depicting the highly frequency dependant transmission-line properties. A system model of a power factor correction (PFC) boost converter was completed by using active device models for diodes, MOSFETs, and the gate driver. In addition, equivalent circuits were used to characterize high frequency impedances of the passive components. A PFC boost converter was built and used to validate the model. The PFC operated at a peak output power of 1 kW, switching at 400 kHz, with a universal input ranging from 90-270 VRMS with unity power factor. The time-domain and EMI frequency spectrum waveforms are experimentally measured and agree very well with the simulated values; within 5 dB for EMI. The transmission-line filter was also manufactured for model verification, and it is tested for the first time with an operating converter: a PFC at 50 W output and 50 VDC input. The small signal characteristics match the model very well. In addition, impedance interactions between the filter, the converter, and the EMI measurement set-up are discussed, evaluated, measured, and improved to minimize undesired resonances and increase low-frequency EMI attenuation. Experimentally measured attenuation provided by the filter in the range from 100 kHz to 100 MHz was 20-50 dBμV. The simulation also shows a similar attenuation, with the exception of one key resonance not seen in the simulation. / Master of Science

No description available.

With the increasing demand for fast, cheaper, and efficient power converters come the need for a single-stage power factor correction (PFC) converter. Various single-stage PFC converter proposed in the literature has the drawback of high DC bus voltage at the input side and together with the shift to wide bandgap switches like GaN drives the converter cost higher. However, an interleaved topology with high-frequency isolation was proposed in this research work due to the drastic reduction in the DC bus voltage and extremely low input current ripple thereby making the need for an EMI filter circuit optional.   Meanwhile, this research work focuses on adapting the proposed topology for a high voltage low current application (EV charger - 400V, 7KW) and low voltage high current application (telecom power supply - 58V,  58A) owing to cost benefits. However, all single-stage PFC are faced with the drawback of second-order (100Hz) output harmonic ripple. Therefore, the design and simulation presented a huge peak to peak ripple of about 50V/3A and 26V/26A for the EV charger and telecom power supply case, respectively. This created the need for the design of a ripple cancellation circuit as the research required a peak to peak ripple of 8V and 200mV for the EV - charger and telecom power supply, respectively.   A novel output passive ripple cancellation technique was developed for the EV charger case due to the ease it offers in terms of control, circuit complexity and extremely low THDi when compared with the active cancellation approach. The ripple circuit reduced the 50V ripple to 431mV with the use of a total of 2.2mF capacitance at the output stage.   Despite designing the passive technique, an active ripple cancellation circuit was designed using a buck converter circuit for the telecom power supply. The active approach was chosen because the passive has a slow response and incurs more loss at a high current level. Adding the active ripple cancellation circuit led to a quasi-single stage LLC PFC converter topology. A novel duty-ratio feedforward control was added to synchronize the PFC control of the input side with the buck topology ripple cancellation circuit. The addition of the ripple circuit with the feedforward control offered a peak to peak ripple of 6.7mV and a reduced resonant inductor current by half.   After analysis, an extremely low THDi of 0.47%, PF of 99.99% and a peak efficiency of 97.1% was obtained for the EV charger case. The telecom power supply offered a THDi of 2.3%, PF of 99.96% with a peak efficiency of 95%.