Neste trabalho foram estudadas as etapas de processo envolvidas na tecnologia Pin-in-Paste (PIP) de soldagem por refusão de componentes convencionais (THCs - Through Hole Components ou Componentes de Furo Passante) em placas de circuito impresso (PCIs), utilizando pasta de solda sem chumbo (lead-free) com liga SAC (Sn-Ag-Cu) de forma a atender as novas exigências ambientais para a montagem eletrônica. Inicialmente foi feito o projeto da PCI de teste com três diferentes componentes THCs e três componentes SMD com encapsulamentos distintos, com o objetivo de reproduzir uma PCI comercial. Foram gerados dois diâmetros de furos diferentes para inserir os THCs, possibilitando o estudo da variação de preenchimento com solda no PTH. Foi proposta uma equação para o cálculo do volume de pasta de solda a ser impresso sobre os furos no processo de montagem. A partir desta equação foram calculadas as dimensões dos furos do estêncil para a PCI de teste. Os parâmetros de impressão foram otimizados em função da variação de pressão e da velocidade do rodo. Duas curvas de refusão foram utilizadas, uma convencional e outra otimizada para verificar a variação na geração de defeitos. A impressão de pasta de solda ficou superior ao projetado, o que resultou em todas as amostras terem solda acima do parâmetro mínimo de aceitabilidade de volume de 75% de preenchimento do PTH. Esta sobre impressão ocasionou defeitos em boa parte dos componentes, excesso de solda nos filetes e resíduos de fluxo na solda nos PTHs. Tais defeitos foram expressivos para todos os THCs, mostrando que o excesso de pasta impressa foi decisivo na geração de defeitos para todas as combinações das variáveis estudadas. Os SMDs tiveram solda aceitável, apresentando apenas alguns casos de excesso de fluxo ou pouca solda em alguns QFPs devido ao uso de ilhas com dimensões maiores que o exigido em norma. O processo de Pin In Paste se mostra viável como substituto da solda onda em linhas de montagem para placas com SMDs e THCs, mas estudos posteriores deverão ser realizados para a geração de um modelo confiável de projeto de PCIs e estêncil com solda lead-free para que tal processo seja utilizado em grande escala na indústria. / This study describes the process steps involved in Pin-in-Paste (PIP) reflow soldering technology in printed circuit boards (PCBs) using lead-free solder paste with SAC alloy (Sn-Ag-Cu) in order to attend new environmental requirements for the electronics assembly. Initially it was designed a PCB test with three different THCs (Through Hole Component) and three different SMD (Surface Mount Device) packages in order to reproduce a commercial board. It was generated two different diameters of holes to insert the THCs, aiming to study the solder fill variation in PTH. An equation was proposed for calculating the volume of solder paste to be printed over the holes in the assembly process. From this equation it was calculated the dimensions of the holes of the stencil. The printing parameters were optimized according to the variation of pressure and speed of the squeegee. Two reflow curves were used in the process, a conventional one and an optimized one to determine the variations in the generation of soldering defects. The printed solder paste volume was higher than projected, which resulted in solder excess, causing defects in most of the components, such as excess solder in the fillet and solder flux residues in PTHs. Such defects were significant for all THCs, showing that the excess paste that was printed caused critical defects for all combinations of variables. Regarding that all samples were above the reflow minimum acceptable volume of 75% coverage of PTH. The SMDs solders were acceptable, with only few cases of solder flux excess. The Pin in Paste process was observed as a good option to replace the wave soldering thermal process for mixed PCBs. Further studies should be conducted to generate a reliable model of PCB and stencil design.

Outer space is a very harsh environment that can cause electronics to not operate as they were originally intended. Aside from the extreme amount of radiation found in space, temperatures can also change very dramatically in a relatively small time frame. In order to test electronics that will be used in this environment, they first need to be tested on Earth under replicated conditions. Vanderbilt University designed a dewar that allows devices to be tested at these extreme temperatures while being radiated. For this thesis, a test setup that met all of the dewar's constraints was designed that would allow a 12-bit, 16-channel analog-to-digital converter to be tested while inside.

In this thesis, vibration induced fatigue life analysis of axial leaded Tantalum &amp / Aluminum capacitors, PDIP and SM capacitors mounted on the printed circuit boards are performed. This approach requires the finite element model, material properties and dynamic characteristics of the PCB. The young modulus of the PCB material is obtained from 3 point bending tests, resonance frequencies are obtained from modal tests and transmissibility&amp / #8217 / s of the PCB are obtained from transmissibility tests which are used as fatigue analysis inputs. Step Stress Tests are performed to obtain failure times of the tested electronic components which are also used as the numerical fatigue analysis inputs. Consecutively, fatigue analysis of a sample PCB used in military systems is aimed since it is important to compare the calculated fatigue damage to estimated life limits in order to determine which component(s), if necessary, must be moved to positions of lower damage . For this purpose, power PCB of the power distribution unit used in Leopard 1 battle tank is examined. Numerical fatigue analysis coupled with accelerated life test whose profile is convenient to military platforms is performed. Furthermore, the effects of eccobond and silicone on the fatigue life of the components are also surveyed since these techniques are common in electronic packaging. In addition, mean-time-to-failure values are obtained for the tested components by using Weibull distribution. Finally, sensitivity analysis is performed to indicate the effect of certain parameters on the fatigue life of a sample axial leaded capacitor.

In this study, the wastewater generated from etching process of the Printed Circuit Board (PCB) was treated by a process including both acidification and coagulation/sedimentation and then followed by the catalytic wet air oxidation (CWAO) over different catalysts (either Pt/SiO2¡PAl2O3 or Pt¡PX/£^-Al2O3) process in series. Although the initial chemical oxygen demand (COD) concentration of the wastewater is as high as 7740-12700 mg/L, the effluent of the pretreatment process was measured to have COD value in ranges of 3050-4260 mg/L. Several re-action parameters, such as reaction temperatures (200-260¢J), oxygen partial pressures (0-3 MPa), and two kinds of catalysts were performed experimentally to investigate the COD reduction of the wastewater during the CWAO process. Both reaction temperature and variety of catalyst are found most effectively on the COD reduction. However, the effect of oxygen partial pressure on the COD reduction is just in little. Results showed that the COD reduction during the CWAO over the Pt¡PX/£^-Al2O3 catalyst process is the most significant, which with a tow-step re-action and both the two reactions do obey first-order reaction kinetics. A change from a higher reaction activity of the CWAO reaction to a slower one implies a decrease of the reaction rate. On basis of our experiments data, the effective operating conditions of CWAO for the COD reduction was observed to be at temperature of 260¢J under oxygen partial pressure of 2.0 MPa and at a retention time period of 60 min. The COD conversion was calculated as high as 75%; however, it could be enhanced up to 78% and 91%, respectively, when the CWAO was conducted in presence of the Pt/SiO2¡PAl2O3 and Pt¡PX/£^-Al2O3 catalysts, respectively. It can be seen that the organic compound of the wastewater was mineralized most completely (with a COD/TOC ratio of 3.7¡Ó0.2) after the CWAO over the Pt¡PX/£^-Al2O3 catalyst process. Furthermore, a higher COD/TOC ratio of 3.9¡Ó0.3 was achieved when the Pt/SiO2¡PAl2O3 catalyst was in presence of the CWAO process, and the primitive WAO process had the highest COD/TOC ratio of 4.8¡Ó0.4. The experimental data showed that both a higher reaction temperature (¡Ù260¢J) and an application of catalyst are more important factors for the min-eralization of the organic compound of the wastewater during the CWAO process. In our investigation, BOD5/COD ratio has been used to assess if the WAO and/or the CWAO process treatment yield products more amenable to biodegradation. The BOD5/COD ratio was 0.68-0.93 when the reaction temperature was above 220¢J and the retention time was as long as 60 min. Unfortunately, the BOD5/COD ratio of the effluent from the CWAO process came out a lower value (0.45-0.65) though it was under the same reaction conditions. It is probable that the biodegradable portion of the organic compounds of the wastewater were decomposed easier during the CWAO process than during the WAO process. In addition, it was found that the products of the wastewater was decomposed partially into CO2 and into some low molecular weigh acids, such as formic acid, acetic acid, propionic acid, etc. The activation energy with respect to COD was calculated to be 38.42 kJ/mole and 83 kJ/mole, respectively, for the first-step reaction and for the second-step reaction, respectively, of the WAO process. It was al-so calculated that the first-step reaction of the CWAO over the Pt/SiO2¡PAl2O3 catalyst process has activation energy of 18.25 kJ/mole and 25.76 kJ/mole is for the second-step reaction. However, 16.05 kJ/mole and 49.61 kJ/mole are calculated for the first-step and the sec-ond-step reactions, respectively, of the CWAO over the Pt¡PX/£^-Al2O3 catalyst process. It can be seen that the application of both the Pt/SiO2¡PAl2O3 and the Pt¡PX/£^-Al2O3 catalysts has a significant effect on reducing the activation energy of the WAO. It was observed that the total COD conversion of the wastewater is as high as 96% and the BOD5/COD ratio of the effluent has been en-hanced up to more than 0.6. The combination of both the CWAO over the Pt¡PX/£^-Al2O3 catalyst and the biological treatment is a promising tech-nique for the PCB¡¦s wastewater treatment to fit the wastewater control regulation in Taiwan, which requests the COD value of the wastewater discharged should be less than 120 mg/L.

The ever-increasing need for higher bandwidth and density is one of the motivations for extensive research on planar optoelectronic structures on printed circuit board (PCB) substrates. Among these applications, optical interconnects have received considerable attention in the last decade. Several optical interconnect techniques, such as free space, guided wave, board level and fiber array interconnects, have been introduced for system level applications. In all planar optoelectronic systems, optical waveguides are crucial elements that facilitate signal routing. Low propagation loss, high reliability and manufacturability are among the requirements of polymer optical waveguides and polymer passive devices on PCB substrates for practical applications. Besides fabrication requirements, reliable characterization tools are needed to accurately and nondestructively measure important guiding properties, such as waveguide propagation loss. In three-dimensional (3D) fully embedded board-level optical interconnects, another key challenge is to realize efficient optical coupling between in-plane waveguides and out-of-plane laser/detector devices. Driven by these motivations, the research presented in this thesis focuses on some fundamental studies of optical interconnects for PCB substrates, e.g., developing low-loss optical polymer waveguides with integrated efficient out-of-plane couplers for optical interconnects on printed circuit board substrates, as well as the demonstration of a novel free-space optical interconnect system by using a volume holographic thin film. Firstly, the theoretical and experimental investigations on the limitations of using mercury i-line ultraviolet (UV) proximity photolithography have been carried out, and the metallization techniques for fine copper line formation are explored. Then, a new type of low-loss polymer waveguides (i.e., capped waveguide) is demonstrated by using contact photolithography with considerable performance improvement over the conventional waveguides. To characterize the propagation properties of planar optical waveguides, a reliable, nondestructive, and real-time technique is presented based on accurately imaging the scattered light from the waveguide using a sensitive charge coupled device (CCD) camera that has a built-in integration functionality. To provide surface normal light coupling between waveguides and optoelectronic devices for optical interconnects, a simple method is presented here to integrate 45° total internal reflection micro-mirrors with polymer optical waveguides by an improved tilted beam photolithography (with the aid of de-ionized water) on PCBs. A new technique is developed for a thin layer of metal coating on the micro-mirrors to achieve higher reflection and coupling efficiency (i.e., above 90%). The combination of the capped waveguide technique and the improved tilted UV exposure technique along with a hard reusable metal mask for metal deposition eliminates the usage of the traditional lift-off process, greatly simplifies the process, and reduces fabrication cost without sacrificing the coating quality. For the study of free-space optical interconnects, a simple system is presented by employing a single thin-film polymeric volume holographic element. One 2-spherical-beam hologram is used to link each point light source with the corresponding photodetector. An 8-channel free-space optical interconnect system with high link efficiency is demonstrated by using a single volume holographic element where 8 holograms are recorded.

Outer space is a very harsh environment that can cause electronics to not operate as they were originally intended. Aside from the extreme amount of radiation found in space, temperatures can also change very dramatically in a relatively small time frame. In order to test electronics that will be used in this environment, they first need to be tested on Earth under replicated conditions. Vanderbilt University designed a dewar that allows devices to be tested at these extreme temperatures while being radiated. For this thesis, a test setup that met all of the dewar's constraints was designed that would allow a 12-bit, 16-channel analog-to-digital converter to be tested while inside.

In this study, the plant layout problem of a worldwide Printed Circuit Board (PCB) producer company is analyzed. Machines are grouped into cells using grouping methodologies of Tabular Algorithm, K-means clustering algorithm, and Hierarchical grouping with Levenshtein distances. Production plant layouts, which are formed by using different techniques, are evaluated using technical and economical indicators.

The goal was to build a machine that could rapidly prototype PCBs using a moving light source and photoresist. The project failed, as the UV light did not make it through the lenses used to concentrate it. Better lenses and a laser would allow it to function better.

Orientador: Marcelo Moreira Ganzarolli / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Mecanica / Made available in DSpace on 2018-07-22T20:18:14Z (GMT). No. of bitstreams: 1 Avelar_AnaCristina_M.pdf: 5757345 bytes, checksum: ab66436b252ec7b8b48d4756dd9e7f42 (MD5) Previous issue date: 1997 / Resumo: Os constantes avanços tecnológicos em eletrônica e informática tem tornado os sistemas eletrônicos cada vez mais compactos, aumentando-se a quantidade de calor a ser removida dos componentes e placas de circuito impresso. Por este motivo, atualmente são exigidos sistemas de dissipação de calor altamente eficientes. Este estudo analisa teórica e experimentalmente a transferência de calor em canais verticais formados por placas de circuito impresso dispostas paralelamente, resfriadas por convecção natural e propõe uma modelagem, baseada em relações existentes na literatura, que busca prever a distribuição de temperaturas em pontos significativos nos canais e placas em função da potência dissipada e da distância entre as placas. Este estudo visa também analisar os efeitos do aquecimento não-uniforme das placas que formam o canal. Na simulação teórica, devido à pequena espessura da placa o gradiente de temperatura ao longo da espessura da mesma foi desprezado e resolveu-se numericamente a equação de transferência de calor em coordenadas cartesianas bidimensionais e em regime permanente. Equacionou-se balanços de energia para os componentes e para o ar no canal e o problema foi resolvido numericamente através de um programa computacional. As placas de circuito impresso utilizadas nos testes experimentais, concebidas exclusivamente para fins de estudos térmicos, possuem uma base de epóxi com 25 resistores discretamente distribuídos sobre sua superfície de 200x164mm. Realizou-se testes com aquecimento uniforme e não-uniforme, variando-se a potência por componentes nas placas. Variou-se também as potências por placas e as distâncias entre as mesmas. Testou-se as potências de 2, 4,6 e 8 W e as distâncias entre placas de 12,24, e 48mm. Verificou-se boa concordância entre os resultados numéricos e experimentais, principalmente para a menor distância entre placas, 12 mm, onde a diferença entre os resultados teóricos e experimentais foi muito pequena / Abstract: The constant technological advances in electronics and computations have made the electronic system increasingly more compact, thus increasing the amount of heat to be removed ITomthe components and printed circuit boards. For this reason, highly efficient system of heat removal are presently required. This study analyses both theoretically and experimentallyheat transfer in an array of vertical parallel printed circuit boards, cooled off by natural convection and proposes a modeling, based on correlation found in literature which tries to predict temperature distribution in significant places in the channels and boards as regards dissipated power and distance among boards. This study also aims at analyzing nonuniform heating effets of the channel made boards. In the theoritical simulation, due to the board' s small thickness, the temperature gradient across the board has been neglected, and the equation of heat transfer in two-dimensional Cartesian was numericallysolved, and on a steady state. Energy balances for the componentes were formulated, and the problem was numerically solved by a computer programo The printed circuit boards used in the experimental tests, manufactured speciallyfor heat trasnfer studies have an epoxy basis with 25 resistors discretely distributed on 200 x 164 mm. Uniform and non-uniform heating tests were performed, thus a variation of power and distance among them had a variation. The 2, 4, 6 and 8 W power and distance among 12, 24 and 48 mm boards were tested. Good agreements between numerical and experimentalresults were observed, mainlyfor the smaller distance among boards, 12 mm, the differencesbetween the theoretical and experimentalresults were small / Mestrado / Termica e Fluidos / Mestre em Engenharia Mecânica

L’objectif de cette thèse est de concevoir un réseau réflecteur à dépointage électronique à 20 GHz pour des applications de communication avec des drones (Unmanned Aerial System). Le principe de fonctionnement des réseaux réflecteurs est similaire à celui d’une antenne parabolique. La principale différence concerne la forme du réflecteur. En effet les panneaux des réseaux réflecteurs sont plans contrairement à la parabole. Le panneau réflecteur se compose de cellules élémentaires qui sont utilisées pour contrôler la phase réfléchie de l’onde d’incidente. Le contrôle de la phase au niveau de la cellule élémentaire nous permet de focaliser le diagramme de rayonnement dans la direction souhaitée. Dans cette thèse, la solution retenue est l’utilisation de diodes PIN. Cette dernière a fait l’objet de nombreuses études que ce soit au niveau laboratoire mais également industriel et possède des atouts intéressant en terme de performance et de coût. L'étude montre que d'avoir un niveau de correction élevée ne garantit pas la meilleure performance parce qu'il faut aussi considérer les pertes dans l'élément actif lui-même (dans notre cas, il s’agit des pertes dans les diodes PIN). Dans l’avenir, il serait nécessaire de modifier la position de la diode afin de rendre la fabrication plus aisée. Dans ce cas il faudra retravailler sur les lignes de polarisation et aussi les géométries du stub et des vias. Il sera peut-être nécessaire de déplacer la diode à l'extérieur du substrat en face l'arrière de la cellule par exemple. Quand les réseaux réflecteurs seront fabriqués, ils pourront être directement testés avec le contrôleur de diode fabriqué. / The objective of this project is to design and fabricate a reconfigurable reflectarray with beam scanning capability at 20 GHz for unmanned aerial system (UAS) communication link. Reflectarray is a type of antenna that shares similar functionality to parabolic reflector antenna. The main difference is the physical and geometry appearance of the antenna where reflectarray has flat reflecting panel instead of parabolic reflector. The reflecting panel consists of elementary cell, which is used to control the reflected phase of the incident wave. By controlling the reflected phase on each elementary cell, the radiation pattern of the antenna can be focused to any desired direction. PIN diode technology is chosen as the preferred solution in the context of this project because it is already proven working in the industry and research fields. In house reflectarray simulator has been developed from the simulation, having high correction order will not necessarily improve the performance because the loss inside in active element must also be considered. In the short-term period, the modification on the elementary cell diode polarization line will enable the reflectarray to be fabricated and measured because the current design cannot be fabricated by the manufacturer contrary to their first statement due to position of the diode in the middle of substrates. The modification requires the p-i-n diode to be moved at the backside of the elementary cell and some geometry adjustments are needed for the phase delay line and the via. Once the reflectarray is fabricated, it can be tested directly with the diode controller that is already validated and shown to be working well.