Uždengtos geometrijos atrinkimas – tai būdas nustatyti geometriją, kuri yra uždengta su kita geometrija ir dėl to gali būti nevaizduojama, nes neturės jokios įtakos vaizduojamam paveikslui. Tokios geometrijos nevaizdavimas didina vaizdavimo procedūros našumą. Egzistuoja eilė uždengtos geometrijos nustatymo būdų, iš kurių vienas yra hierarchinis uždengtos geometrijos atrinkimo algoritmas. Šiame darbe yra analizuojami uždengtos geometrijos nustatymo būdai bei nagrinėjamos pasirinkto algoritmo veikimo spartinimo galimybės panaudojus DirectCompute technologiją. Ši technologija yra Microsoft DirectX 11 bibliotekų rinkinio dalis, kuri leidžia panaudoti grafinį procesorių bendro pobūdžio skaičiavimams. Darbe iškeltų tikslų pasiekimui yra realizuotos kelios bazinės algoritmo versijos modifikacijos, atliekami modifikuotų versijų veikimo laiko bei įvairių veikimo laiką įtakojančių faktorių tyrimai. Yra aptariami gauti rezultatai bei pateikiamos išvados. / Occlusion culling is a method, which task is to determine geometry occluded with other geometry. Rendering this geometry is useless because it wouldn’t impact rendered picture in any way, so discarding it will improve render time. There are various methods to determine occluded geometry and hierarchical occlusion culling is one of them. This document contains a short summary of these methods, but it’s mainly focused on improving hierarchical occlusion culling algorithm performance by making use of DirectCompute technology. This technology is a part of Microsoft DirectX 11 API, which helps the developer to use graphics processor for general-purpose computation. Main goal is reached by performing in-depth analysis of implemented hierarchical occlusion culling algorithm modifications. This analysis consists of both general performance and various performance-related analyses. Further down the road conclusions and recommendations are given based on performed work and overall results.

Pagrindinė kompiuterio sudedamoji dalis yra duomenų traktas. Jį sudaro keletas registrų, dvi arba trys magistralės bei vienas ar keli funkciniai blokai, tokie kaip aritmetinis ir loginis įrenginys. Pagrindinis ciklas susideda iš keleto operandų iškvietimo, kurie yra registruose ir jų perdavimui magistralėmis į ALĮ ar kitą funkcinį bloką. Po šių operacijų įvykdymo rezultatai yra saugomi atgal į registrus. Duomenų traktas gali būti valdomas eiliškumo tvarka, kuri iškviečia mikroinstrukcijas iš atminties. Kiekvieną mikroinstrukciją sudaro bitai, kurie yra valdomi duomenų trakto vieno ciklo metu. Šie bitai nustato kuriuos operandus reikia išrinkti, kokią operaciją reikia atlikti ir ką reikia daryti su rezultatais. IJVM – mašina su stekine organizacija ir vieno baito operacijos kodu, kuris padeda žodžius į steką, taip pat juos paima iš steko ir atlieka įvairias operacijas su žodžiais iš steko. Kalbant apie kompiuterių produktyvumą galima paminėti, jog pagrindinis metodas yra dalinės atminties naudojimas. Tiesioginio atvaizdavimo ir asociatyvi tarpin÷ atmintis plačiai taikoma kreipimosi į atmintį pagreitinimui. Nagrinėti trys pavyzdžiai, Pentium II, UltraSPARC II ir picoJava II daugumoje atvejų skiriasi vieni nuo kitų, tačiau vykdant instrukcijas jie yra labai panašūs. Pentium II turi CISC tipo instrukcijas, kurias padalina į mikroinstrukcijas. Jos yra apdirbamos superskaliarinės architektūros instrukcijos su šakojimosi numatymu. UltraSPARC II yra modernus 64 bitų procesorius su... [toliau žr. visą tekstą] / The main component of the computer is a data path. It consists of several registers, two or three buses, one or more functional blocks, such as ALU. The primary cycle consists of a call of operands from registers. Operands are transferred to ALU by buses. After these operations, results are saved in again in the registers. The data path can be controlled by the sequence method, which calls the microinstruction from the memory. Every microinstruction consists of bits, which are controlled by data path in one cycle. These bits determine which operands they have to choose, what you need to execute and what to do with the results. IJVM – a machine with stack organization. It has one-byte operations, which places words on the stack, pushing them from the stack and carry out various operations with words from the stack. Our three examples, Pentium II, UltraSPARC II and picoJava II in many ways differs from each other, but surprisingly are similar in executing instructions. Pentium II takes CISC instructions and splits them into microinstructions. UltraSPARC II is a modern 64 – bit processor with instruction set of RISC. PicoJava II is a simple designed processor for lowcost devices. It has no such features like dynamic branch prediction, but it can execute JVM instructions rather quickly like its done with RISC instructions. All three machines contain similar functional blocks that can process three microinstructions when they pass through the conveyor.

This thesis investigates using processor-in-loop techniques with non-real-time electro-magnetic transient simulation software for designing microcontroller-based systems. The behaviour of a microcontroller is included in the simulation by directly integrating the target microcontroller into an EMTP co-simulation. Additionally, to assist the design process, the optimization functionality of the EMTP program is extended to the microcontroller algorithm. Since non-realtime simulation does not require specialized test hardware to accurately simulate systems, it is both cheaper and able to be used earlier in the controller design process then hardware-in-loop real-time simulation. A component is created in the PSCAD / EMTDC program to integrate a generic controller running an arbitrary periodic algorithm into an EMTP simulation. The component operation is verified by creating a co-simulation of a three-phase induction motor V / f. speed control. The co-simulation results match the behaviour of the resulting system under a fairly broad range of operating conditions, highlighting the applicability of the technique.

VecTor is a suite of computer programs developed for the nonlinear finite element analysis of reinforced concrete structures. Due to the substantial nature of output data produced by the programs, accessing pertinent analysis information is not easily accomplished. A graphics-based post-processor would greatly improve the overall utility of the VecTor programs by allowing the multitude of information to be visually displayed and manipulated for the purposes of data synthesis and rapid verification of results. The intent of this manual is to demonstrate a post-processor program which reads and displays the results of VecTor-based analyses in a robust and straightforward manner. The proposed post-processor program, named Janus, will provide the user with the capability to display both local and global response characteristics. Janus will allow the user to comprehensively recall and manipulate structural analysis results on a model-wide basis as well as display pertinent information for individually specified elements of interest.

VecTor is a suite of computer programs developed for the nonlinear finite element analysis of reinforced concrete structures. Due to the substantial nature of output data produced by the programs, accessing pertinent analysis information is not easily accomplished. A graphics-based post-processor would greatly improve the overall utility of the VecTor programs by allowing the multitude of information to be visually displayed and manipulated for the purposes of data synthesis and rapid verification of results. The intent of this manual is to demonstrate a post-processor program which reads and displays the results of VecTor-based analyses in a robust and straightforward manner. The proposed post-processor program, named Janus, will provide the user with the capability to display both local and global response characteristics. Janus will allow the user to comprehensively recall and manipulate structural analysis results on a model-wide basis as well as display pertinent information for individually specified elements of interest.

This thesis presents new simulation techniques designed to speed up the simulation of microprocessor systems. The advanced simulation techniques may be applied to the simulator class which employs dynamic binary translation as its underlying technology. This research supports the hypothesis that faster simulation speeds can be realized by translating larger sections of the target program at runtime. The primary motivation for this research was to help facilitate comprehensive design-space exploration and hardware/software co-design of novel processor architectures by reducing the time required to run simulations. Instruction set simulators are used to design and to verify new system architectures, and to develop software in parallel with hardware. However, compromises must often be made when performing these tasks due to time constraints. This is particularly true in the embedded systems domain where there is a short time-to-market. The processing demands placed on simulation platforms are exacerbated further by the need to simulate the increasingly complex, multi-core processors of tomorrow. High speed simulators are therefore essential to reducing the time required to design and test advanced microprocessors, enabling new systems to be released ahead of the competition. Dynamic binary translation based simulators typically translate small sections of the target program at runtime. This research considers the translation of larger units of code in order to increase simulation speed. The new simulation techniques identify large sections of program code suitable for translation after analyzing a profile of the target program’s execution path built-up during simulation. The average instruction level simulation speed for the EEMBC benchmark suite is shown to be at least 63% faster for the new simulation techniques than for basic block dynamic binary translation based simulation and 14.8 times faster than interpretive simulation. The average cycle-approximate simulation speed is shown to be at least 32% faster for the new simulation techniques than for basic block dynamic binary translation based simulation and 8.37 times faster than cycle-accurate interpretive simulation.

Constant False Alarm Rate (CFAR) Processors are important for applications where thousands of detection tests are made per second, such as in radar. This thesis introduces a new method for CFAR threshold estimation that is particularly applicable to sound source detection with distributed microphone systems. The novel CFAR Processor exploits the near symmetry about 0 for the acoustic pixel values created by steered-response coherent power in conjunction with a partial whitening preprocessor to estimate thresholds for positive values, which represent potential targets. To remove the low frequency components responsible for degrading CFAR performance, fixed and adaptive high-pass filters are applied. A relation is proposed and it tested the minimum high-pass cut-off frequency and the microphone geometry. Experimental results for linear, perimeter and planar arrays illustrate that for desired false alarm (FA) probabilities ranging from 10-1 and 10-6, a good CFAR performance can be achieved by modeling the coherent power with Chi-square and Weibull distributions and the ratio of desired over experimental FA probabilities can be limited within an order of magnitude.

Rotor dynamic analysis, which requires extensive amount of data and rigorous analytical processing, has been eased by the advent of powerful and affordable digital computers. By incorporating the processor and a graphical interface post processor in a single set up, this program offers a consistent and efficient approach to rotor dynamic analysis. The graphic user interface presented in this program effectively addresses the inherent complexities of rotor dynamic analyses by linking the required computational algorithms together to constitute a comprehensive program by which input data and the results are exchanged, analyzed and graphically plotted with minimal effort by the user. Just by selecting an input file and appropriate options as required, the user can carry out a comprehensive rotor dynamic analysis (synchronous response, stability analysis, critical speed analysis with undamped map) of a particular design and view the results with several options to save the plots for further verification. This approach helps the user to modify the design of turbomachinery quickly, until an efficient design is reached, with minimal compromise in all aspects.

Percent Moisture Content (MC %) of wood is defined to be the weight of the moisture in the wood divided by the weight of the dry wood times 100%. Equilibrium Moisture Content (EMC), moisture content at environmental equilibrium is a very important metric affecting the performance of wood in many applications. For best performance in many applications, the goal is to maintain this value between 6% and 8%. EMC value is a function of the temperature and the relative humidity of the surrounding air of wood. It is very important to maintain this value while processing, storing or finishing the wood. This thesis develops a special purpose sensor and processor system to be implemented as a small hand-held device used to sense, calculate and display the value of EMC of wood depending on surrounding environmental conditions. Wood processing industry personnel would use the hand-held EMC calculating and display device to prevent many potential problems that can show significant affect on the performance of wood. The design of the EMC device requires the use of sensors to obtain the required inputs of temperature and relative humidity. In this thesis various market available sensors are compared and appropriate sensor is chosen for the design. The calculation of EMC requires many arithmetic operations with stringent precision requirements. Various arithmetic algorithms and systems are compared in terms of meeting required arithmetic functionality, precision requirements, and silicon implementation area and gate count, and a suitable choice is made. The resulting processor organization and design is coded in VHDL using the Xilinx ISE 6.2.03i tool set. The design is synthesized, validated via VHDL virtual prototype simulation, and implemented to a Xilinx Spartan2E FPGA for experimental hardware prototype testing and evaluation. It is tested over various ranges of temperature and relative humidity. Comparison of experimentally calculated EMC values with the theoretical values of EMC derived for corresponding temperature and relative humidity points resulted in validation of the EMC processor architecture, functional performance and arithmetic precision requirements.

This study analyzed the perceptions of Kentucky Homebased Processors and Microprocessors of the benefits of and barriers to developing and selling value-added products. The final sample consisted of 141 participants, 60.5% (n=72) of which were from Central KY, 26.9% (n=32) were from Western KY, and 12.6% (n=15) were from Eastern KY. Overall, participants seemed to feel that their value-added products were successful in many different benefit categories. The primary barriers to developing value-added products were lack of time, lack of funding, and lack of legal knowledge. The primary barriers to utilizing program resources for farmers were not having enough time, being unaware of the services offered, and programs being too far away. The information found by this study can be used to determine the addressable needs in different regions of Kentucky and assist programs in making their services more available and applicable to Kentucky farm entrepreneurs.