Cheung Chak Chung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 101-114). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgments --- p.iii / Vita --- p.v / Table of Contents --- p.vi / List of Figures --- p.x / List of Tables --- p.xiv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Aims and Contribution --- p.4 / Chapter 1.3 --- Thesis Overview --- p.5 / Chapter 2 --- VLSI Design Cycle --- p.6 / Chapter 2.1 --- Logic Synthesis --- p.7 / Chapter 2.1.1 --- Logic Minimization --- p.8 / Chapter 2.1.2 --- Technology Mapping --- p.8 / Chapter 2.1.3 --- Testability --- p.8 / Chapter 2.2 --- Physical Design Synthesis --- p.8 / Chapter 2.2.1 --- Partitioning --- p.9 / Chapter 2.2.2 --- Floorplanning & Placement --- p.10 / Chapter 2.2.3 --- Routing --- p.11 / Chapter 2.2.4 --- "Compaction, Extraction & Verification" --- p.12 / Chapter 2.2.5 --- Physical Design of FPGAs --- p.12 / Chapter 3 --- Alternative Wiring --- p.13 / Chapter 3.1 --- Introduction --- p.13 / Chapter 3.2 --- Notation and Definitions --- p.15 / Chapter 3.3 --- Application of Rewiring --- p.17 / Chapter 3.3.1 --- Logic Optimization --- p.17 / Chapter 3.3.2 --- Timing Optimization --- p.17 / Chapter 3.3.3 --- Circuit Partitioning and Routing --- p.18 / Chapter 3.4 --- Logic Optimization Analysis --- p.19 / Chapter 3.4.1 --- Global Flow Optimization --- p.19 / Chapter 3.4.2 --- OBDD Representation --- p.20 / Chapter 3.4.3 --- Automatic Test Pattern Generation (ATPG) --- p.22 / Chapter 3.4.4 --- Graph Based Alternative Wiring (GBAW) --- p.23 / Chapter 3.5 --- Augmented GBAW --- p.26 / Chapter 3.6 --- Logic Optimization by using GBAW --- p.28 / Chapter 3.7 --- Conclusions --- p.31 / Chapter 4 --- Multi-way Partitioning using Rewiring Techniques --- p.33 / Chapter 4.1 --- Introduction --- p.33 / Chapter 4.2 --- Circuit Partitioning Algorithm Analysis --- p.38 / Chapter 4.2.1 --- The Kernighan-Lin (KL) Algorithm --- p.39 / Chapter 4.2.2 --- The Fiduccia-Mattheyses (FM) Algorithm --- p.42 / Chapter 4.2.3 --- Geometric Representation Algorithm --- p.46 / Chapter 4.2.4 --- The Multi-level Partitioning Algorithm --- p.49 / Chapter 4.2.5 --- Hypergraph METIS - hMETIS --- p.51 / Chapter 4.3 --- The GBAW Partitioning Algorithm --- p.53 / Chapter 4.4 --- Experimental Results --- p.56 / Chapter 4.5 --- Conclusions --- p.58 / Chapter 5 --- Optimum FPGA Switch-Box Designs - HUSB --- p.62 / Chapter 5.1 --- Introduction --- p.62 / Chapter 5.2 --- Background and Definitions --- p.65 / Chapter 5.2.1 --- Routing Architectures --- p.65 / Chapter 5.2.2 --- Global Routing --- p.67 / Chapter 5.2.3 --- Detailed Routing --- p.67 / Chapter 5.3 --- FPGA Router Comparison --- p.69 / Chapter 5.3.1 --- CGE --- p.69 / Chapter 5.3.2 --- SEGA --- p.70 / Chapter 5.3.3 --- TRACER --- p.71 / Chapter 5.3.4 --- VPR --- p.72 / Chapter 5.4 --- Switch Box Design --- p.73 / Chapter 5.4.1 --- Disjoint type switch box (XC4000-type) --- p.73 / Chapter 5.4.2 --- Anti-symmetric switch box --- p.74 / Chapter 5.4.3 --- Universal Switch box --- p.74 / Chapter 5.4.4 --- Switch box Analysis --- p.75 / Chapter 5.5 --- Terminology --- p.77 / Chapter 5.6 --- "Hyper-universal (4, W)-design analysis" --- p.82 / Chapter 5.6.1 --- "H3 is an optimum (4, 3)-design" --- p.84 / Chapter 5.6.2 --- "H4 is an optimum (4,4)-design" --- p.88 / Chapter 5.6.3 --- "Hi is a hyper-universal (4, i)-design for i = 5,6,7" --- p.90 / Chapter 5.7 --- Experimental Results --- p.92 / Chapter 5.8 --- Conclusions --- p.95 / Chapter 6 --- Conclusions --- p.99 / Chapter 6.1 --- Thesis Summary --- p.99 / Chapter 6.2 --- Future work --- p.100 / Chapter 6.2.1 --- Alternative Wiring --- p.100 / Chapter 6.2.2 --- Partitioning Quality --- p.100 / Chapter 6.2.3 --- Routing Devices Studies --- p.100 / Bibliography --- p.101 / Chapter A --- 5xpl - Berkeley Logic Interchange Format (BLIF) --- p.115 / Chapter B --- Proof of some 2-local patterns --- p.122 / Chapter C --- Illustrations of FM algorithm --- p.124 / Chapter D --- HUSB Structures --- p.127 / Chapter E --- Primitive minimal 4-way global routing Structures --- p.132

Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2006. / Includes bibliographical references (p. 63-71).

FPGA clock frequencies are slow enough that only a fraction of the interconnect’s bandwidth is used. By exploiting this bandwidth, the transfer of large amounts of data can be greatly accelerated. Alternatively, it may also be possible to save area on fixed-bandwidth links by using on-chip serial signaling. For datapath-intensive designs which operate on words instead of bits, this can reduce wiring congestion as well. This thesis proposes relatively simple circuit-level modifications to FPGA interconnect to enable high-bandwidth communication. High-level area estimates indicate a potential interconnect area savings of 10 to 60% when serial links are used. Two interconnect pipelining techniques, wave pipelining and surfing, are adapted to FPGAs and compared against each other and against regular FPGA interconnect in terms of throughput, reliability, area, power, and latency. Source-synchronous signaling is used to achieve high data rates with simple receiver design. Statistical models for high-frequency power supply noise are developed and used to estimate the probability of error of wave pipelined and surfing links as a function of link length and operating speed. Surfing is generally found to be more reliable and less sensitive to noise than wave pipelining. Simulation results in a 65nm process demonstrate a throughput of 3Gbps per wire across a 50-stage, 25mm link.

Thesis (M.S.)--University of North Texas, August, 2009. / Title from title page display. Includes bibliographical references.

Thesis (Ph. D.)--Worcester Polytechnic Institute. / Keywords: computer arithmetic; elliptic curves; cryptography. Includes bibliographical references (p. 299-305).

Thesis (Ph. D.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2004. / Includes bibliographical references (p. 143-149).

Thesis (Ph. D.)--University of California, Riverside, 2008. / Includes abstract. Title from first page of PDF file (viewed March 8, 2010). Available via ProQuest Digital Dissertations. Includes bibliographical references (p. 150-168). Also issued in print.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, December 2003. / Thesis advisor(s): Herschel H. Loomis, Jr., Alan A. Ross. Includes bibliographical references (p. 241-243). Also available online.

Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010. / Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Ghovanloo, Maysam. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2003. / Includes bibliographical references (p. 229-232).