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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
51

Using duplication with compare for on-line error detection in FPGA-based designs /

McMurtrey, Daniel Lee, January 2006 (has links) (PDF)
Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2006. / Includes bibliographical references (p. 61-63).
52

Optimizing scalar multiplication for Koblitz curves using hybrid FPGAs /

Głuszek, Gregory A. January 2009 (has links)
Thesis (M.S.)--Rochester Institute of Technology, 2009. / Typescript. Includes bibliographical references (leaves 93-95).
53

A novel partial reconfiguration methodology for FPGAs of multichip systems /

Galindo, Juan Manuel. January 2008 (has links)
Thesis (M.S.)--Rochester Institute of Technology, 2008. / Typescript. Includes bibliographical references (leaves 37-40).
54

Design of custom instruction set for FFT using FPGA-based Nios processors

Sunkara, Divya Lakshmi. Meyer-Baese, U. January 2004 (has links)
Thesis (M.S.)--Florida State University, 2004. / Advisor: Dr. Uwe Meyer-Baese, Florida State University, College of Engineering, Dept. of Electrical and Computer Engineering. Title and description from dissertation home page (viewed Sept. 15, 2005). Document formatted into pages; contains ix, 108 pages. Includes bibliographical references.
55

Higher radix floating-point representations for FPGA-based arithmetic /

Catanzaro, Bryan C. January 2005 (has links) (PDF)
Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2005. / Includes bibliographical references (p. 81-86).
56

Design and evaluation of an "FPGA based" hardware accelerator for elliptic curve cryptography point multiplication a thesis presented to the faculty of the Graduate School, Tennessee Technological University /

Gwalani, Kapil A., January 2009 (has links)
Thesis (M.S.)--Tennessee Technological University, 2009. / Title from title page screen (viewed on June 25, 2010). Bibliography: leaves 93-96.
57

Development test suite for FPGA TekBot learning platform /

Lai, Gerald. January 1900 (has links)
Thesis (M.S.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 73-76). Also available on the World Wide Web.
58

An FPGA-based 3D backprojector

Sorokin, Nikolay. Unknown Date (has links) (PDF)
University, Diss., 2003--Saarbrücken.
59

AN APPROACH TOWARDS HDL MODEL GENERATION FOR THE MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY

RAMASWAMY, EASWAR SINGANELLORE 03 April 2006 (has links)
No description available.
60

All Digital FM Demodulator

Nair, Kartik 20 September 2019 (has links)
The proposed demodulator is an all-digital implementation of a FM demodulator. The proposed design intends to implement a FM demodulator for high-speed applications, which makes the requirements for analog components minimal. The proposed circuit is an all-digital quadrature demodulator, where the individual components have been implemented without using any multipliers. The topology uses a Pulse width modulation (PWM) block to avoid the need for a DAC. The Xilinx virtex-7 FPGA has been used as the reference device for the work. The circuit is validated through behavioral simulations and the results conclude the proposed circuit demodulates the targeted FM channel and provides the spectrum information for the targeted FM channel / Master of Science / With the rise in popularity of reconfigurable hardware, such as FPGAs, digital signal processing has become one of the most widespread usage of such devices. The major advantage of using FPGAs for implementing signal processing algorithms is that they provide very less time to market and can be re-modeled or modified in easily. Moreover, the netlists designed for FPGAs can be easily translated to ASICs. As wireless communication has become omnipresent, modulation and demodulation schemes have become an area of great interest. With the increase in data rates for the modern-day communication systems, the digital implementation of these algorithms is becoming more and more common. This is further aided by the advancements in high-speed ADCs and the Electronic Design Automation (EDA) tools, which have made the usage of FPGAs lot more feasible and a lot more efficient. This work discusses the demodulation scheme for one of the most widespread modulation algorithms, Frequency Modulation (FM). An all-digital FM demodulator design is proposed for highspeed implementation on FPGAs. The proposed design is an all-digital quadrature I-Q based demodulator.

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