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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
81

Embedded soft-core processor-based built-In self-test of field programmable gate arrays

Dutton, Bradley Fletcher. Stroud, Charles E. January 2010 (has links)
Thesis--Auburn University, 2010. / Abstract. Includes bibliographic references (p.162-167).
82

Reliable high-throughput FPGA interconnect using source-synchronous surfing and wave pipelining

Teehan, Paul Leonard 05 1900 (has links)
FPGA clock frequencies are slow enough that only a fraction of the interconnect’s bandwidth is used. By exploiting this bandwidth, the transfer of large amounts of data can be greatly accelerated. Alternatively, it may also be possible to save area on fixed-bandwidth links by using on-chip serial signaling. For datapath-intensive designs which operate on words instead of bits, this can reduce wiring congestion as well. This thesis proposes relatively simple circuit-level modifications to FPGA interconnect to enable high-bandwidth communication. High-level area estimates indicate a potential interconnect area savings of 10 to 60% when serial links are used. Two interconnect pipelining techniques, wave pipelining and surfing, are adapted to FPGAs and compared against each other and against regular FPGA interconnect in terms of throughput, reliability, area, power, and latency. Source-synchronous signaling is used to achieve high data rates with simple receiver design. Statistical models for high-frequency power supply noise are developed and used to estimate the probability of error of wave pipelined and surfing links as a function of link length and operating speed. Surfing is generally found to be more reliable and less sensitive to noise than wave pipelining. Simulation results in a 65nm process demonstrate a throughput of 3Gbps per wire across a 50-stage, 25mm link.
83

An FPGA-based digital logic core for ATE support and embedded test applications

Davis, Justin S. 08 1900 (has links)
No description available.
84

Floating-gate-programmable and reconfigurable, digital and mixed-signal systems

Wunderlich, Richard Bryan 22 May 2014 (has links)
This body of work as whole has the theme of using floating-gates and reconfigurable systems to explore and implement non-traditional computing solutions to difficult problems. Various computational methodologies are used simultaneously to solve problems by mapping pieces of them to the appropriate type of computer. There exists no systematic approach to simultaneously apply analog, digital, and neuromorphic techniques to solving general problems. Typically, this is a very difficult task, and one that few attempt to undertake. However, when done right, solutions can be found with orders-of-magnitude improvement over existing solutions restricted to using only one type computational domain. To that end, I have helped build large and complicated reconfigurable systems (and software tools for helping to use these systems) capable of implementing solutions to problems in all three of those domains simultaneously. These systems are used to explore and implement these cross domain solutions to difficult problems. The earlier work was involved with simply applying floating-gate technology to improving the building blocks of digital systems. Through that early work a new logic family built from floating-gate transistors was discovered, a Logical Effort compatible power analysis technique was developed, and low power floating-gate based FPGA was implemented. This work was then merged with existing research in the group involving solving problems using reconfigurable analog, and neuromorphic techniques. Thus converging on the mentioned systems that allow one to solve problems using techniques from all three domains: analog, neuromorphic, and digital.
85

Global Positioning System signal acquisition and tracking using field programmable gate arrays

Alaqeeli, Abdulqadir A. January 2002 (has links)
Thesis (Ph. D.)--Ohio University, November, 2002. / Title from PDF t.p. Includes bibliographical references (leaves 98-105).
86

Reconfigurable design for pattern recognition using field programmable gate arrays

Sareen, Aman. January 1999 (has links)
Thesis (M.S.)--Ohio University, November, 1999. / Title from PDF t.p.
87

Built-in self-test of logic resources in field programmable data arrays using partial reconfiguration

Dhingra, Sachin Stroud, Charles E. January 2006 (has links) (PDF)
Thesis(M.S.)--Auburn University, 2006. / Abstract. Vita. Includes bibliographic references.
88

Built-In Self-Test of programmable resources in microcontroller based System-on-Chips

Sunwoo, John, Stroud, Charles E. January 2005 (has links) (PDF)
Thesis(M.S.)--Auburn University, 2005. / Abstract. Vita. Includes bibliographic references.
89

A comparative study of high speed adders

Bhupatiraju, Raja D. V. January 1999 (has links)
Thesis (M.S.)--Ohio University, March, 1999. / Title from PDF t.p.
90

Bit-stream signal processing on FPGA

Ng, Chiu-wa. January 2009 (has links)
Thesis (Ph. D.)--University of Hong Kong, 2009. / Includes bibliographical references (p. 90-98) Also available in print.

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