Mannheim, Univ., Diss., 2006.

Thesis (Ph. D.)--University of Glasgow, 2003. / Includes bibliographical references. Print version also available.

Recently, the more widespread use of three-dimensional (3-D) imaging modalities, such as magnetic resonance imaging (MRI), computed tomography (CT), positron emission tomography (PET), and ultrasound (US) have generated a massive amount of volumetric data. These have provided an impetus to the development of other applications, in particular telemedicine and teleradiology. In these fields, medical image compression is important since both efficient storage and transmission of data through high-bandwidth digital communication lines are of crucial importance. Despite their advantages, most 3-D medical imaging algorithms are computationally intensive with matrix transformation as the most fundamental operation involved in the transform-based methods. Therefore, there is a real need for high-performance systems, whilst keeping architectures exible to allow for quick upgradeability with real-time applications. Moreover, in order to obtain efficient solutions for large medical volumes data, an efficient implementation of these operations is of significant importance. Reconfigurable hardware, in the form of field programmable gate arrays (FPGAs) has been proposed as viable system building block in the construction of high-performance systems at an economical price. Consequently, FPGAs seem an ideal candidate to harness and exploit their inherent advantages such as massive parallelism capabilities, multimillion gate counts, and special low-power packages. The key achievements of the work presented in this thesis are summarised as follows. Two architectures for 3-D Haar wavelet transform (HWT) have been proposed based on transpose-based computation and partial reconfiguration suitable for 3-D medical imaging applications. These applications require continuous hardware servicing, and as a result dynamic partial reconfiguration (DPR) has been introduced. Comparative study for both non-partial and partial reconfiguration implementation has shown that DPR offers many advantages and leads to a compelling solution for implementing computationally intensive applications such as 3-D medical image compression. Using DPR, several large systems are mapped to small hardware resources, and the area, power consumption as well as maximum frequency are optimised and improved. Moreover, an FPGA-based architecture of the finite Radon transform (FRAT)with three design strategies has been proposed: direct implementation of pseudo-code with a sequential or pipelined description, and block random access memory (BRAM)- based method. An analysis with various medical imaging modalities has been carried out. Results obtained for image de-noising implementation using FRAT exhibits promising results in reducing Gaussian white noise in medical images. In terms of hardware implementation, promising trade-offs on maximum frequency, throughput and area are also achieved. Furthermore, a novel hardware implementation of 3-D medical image compression system with context-based adaptive variable length coding (CAVLC) has been proposed. An evaluation of the 3-D integer transform (IT) and the discrete wavelet transform (DWT) with lifting scheme (LS) for transform blocks reveal that 3-D IT demonstrates better computational complexity than the 3-D DWT, whilst the 3-D DWT with LS exhibits a lossless compression that is significantly useful for medical image compression. Additionally, an architecture of CAVLC that is capable of compressing high-definition (HD) images in real-time without any buffer between the quantiser and the entropy coder is proposed. Through a judicious parallelisation, promising results have been obtained with limited resources. In summary, this research is tackling the issues of massive 3-D medical volumes data that requires compression as well as hardware implementation to accelerate the slowest operations in the system. Results obtained also reveal a significant achievement in terms of the architecture efficiency and applications performance.

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Approved for public release; distribution is unlimited / The harsh radiation environment of space, the propensity for SEUs to perturb the operations of a silicon based electronics, the rapid development of microprocessor capabilities and hence software applications, and the high cost (dollars and time) to develop and prove a system, require flexible, reliable, low cost, rapidly developed system solutions. Consequently, a reconfigurable Triple Modular Redundant (TMR) System-on-a-Chip (SOC) utilizing Field Programmable Gate Arrays (FPGAs) provides a viable solution for space based systems. The Configurable Fault Tolerant Processor (CFTP) is such a system, designed specifically for the purpose of testing and evaluating, on orbit, the reliability of instantiated TMR soft-core microprocessors, as well as the ability to reconfigure the system to support any onboard processor function. The CFTP maximizes the use of Commercial Off-The-Shelf (COTS) technology to investigate a low-cost, flexible alternative to processor hardware architecture, with a Total Ionizing Dose (TID) tolerant FPGA as the basis for a SOC. The flexibility of a configurable processor, based on FPGA technology, will enable on-orbit upgrades, reconfigurations, and modifications to the architecture in order to support dynamic mission requirements. The CFTP payload consists of a Printed Circuit Board (PCB) of 5.3 inches x 7.3 inches utilizing a slightly modified PC/104 bus interface. The initial FPGA configuration will be an instantiation of a TMR processor, with included Error Detection and Correction (EDAC) and memory controller circuitry. The PCB is designed with requisite supporting circuitry including a configuration controller FPGA, SDRAM, and Flash memory in order to allow the greatest variety of possible configurations. The CFTP is currently manifested as a Space Test Program (STP) experimental payload on the Naval Postgraduate School's NPSAT1 and the United States Naval Academy's MidSTAR-1 satellites. / Major, United States Marine Corps

隨著半導體生產工藝的特徵尺寸日益縮小，工藝變化引起的良率損失亦日益顯著。在現場可編程門陣列平臺，一些優化設計方法根據芯片的特定的工藝變化特徵來優化設計以提高時序良率。然而，目前缺乏一種實際的工藝變化特徵提取方法以支持上述優化設計方法。為了滿足這一需求，在文論文的第一部份，我們提出利用環形振盪器來提取商用現場可編程門陣列芯片的工藝變化特徵。該方法可以提取到邏輯單元級別的時序特徵，并進而推測出互聯電路的時序特徵。為了證明該方法的有效性我們在現場可編程門陣列芯片上任意放置兩個結構完全相同的環形振盪器于不同的位置。我們分別通過直接測量和通過分析特徵提取的數據得到兩振盪器的時序差異。對比結果顯示通過分析特徵提取數據，推算結果和實際測量結果僅平均相差10% 以內。我們在Xilinx 公司的Spartan-3e 芯片上實現了該方法，別且在其他Xilinx 的芯片上同樣適用。 / 在本論文的第二部份，我們提出一種利用現場可編程門陣列架構對稱性的方法來系統化的改變設計道路。通過對一個初始設計電路的旋轉和翻轉，我們可以得到八種時序性能相同的候選設計。在隨機工藝變化的存在下，八種候選設計的任何一個都有同樣的可能性被選為針對某一特定芯片的最優設計。如果大批芯片的單一個體都可以確定最優設計，整體性能將大幅度改善。另外，我們提出交換關鍵路徑上的相鄰邏輯單元來進一步提高時序性能通過對二十個測試電路的仿真實驗，我們發現統計時序性能得到了大幅度改善。相比于其他改善時序性能的方法，該方法從設計時間的角度來看更有效率。 / 雖然工藝變換常被認為一種有害的寄生效應，但是它提供了一些應用前景。物理費克隆方程的提出啟發研究人員把芯片的工藝變化的唯一性轉化為芯片的數字身份。在本論文的第三部份，我們提出利用環形振盪器陣列來測量工藝變化，并通過比較振盪器的相對速度來計算芯片數字身份。然而，芯片身份的穩定性是一個普遍的問題，尤其是在考慮到工作環境(如溫度、這墨)改變的情況下。為了解決這一間包我們提出結合使用可配置的環形振盪器以及重新初始化的方法來提高穩定性。改方法同樣在Xilinx 的Spartan-3e 芯片上實現。實驗結果表明該方法大幅度提高了在工作環境變化下芯片身份的穩定性。 / As semiconductor manufacturing continues towards reduced feature size, yield loss induced by process variation becomes increasingly significant. On the platform of field programmable field array (FPGA), several works proposed to improve timing yield by optimizing design implementation based on chip-specific variation distribution, which are generally defined as variation aware design (VAD) methods. However, there is a lack of practical variation characterization method to facilitate the invented VAD methods. To fulfill this demand, in the first part of this thesis, we proposed to characterize delay variation by measuring the loop delay of ring oscillator (RO) on commercial FPGAs. By comparing the difference of loop delays for ROs with slightly different structures, the logic element (LE) delay can be explicitly characterized. The delays of interconnect circuits can be further derived with existing LE delay information and additional measurements. To evaluate the effectiveness of the proposed variation characterization, two ROs with identical structure are arbitrarily placed at different locations on an FPGA chip. The difference of the loop delays between two ROs can be both directly measured and estimated by characterization results. Taking measurement results as references, the error rate of estimation by characterization results is less than 10% on average. The proposed characterization method is implemented on Xilinx Spartan-3e FPGA chips. Without loss of generality, the proposed method can be also adopted on other Xilinx FPGA devices. / In the second part of this thesis, we proposed to systematically manipulates FPGA post-layout circuits by using FPGA architectural symmetry. Eight timing equivalent “candidate configurations“ can be obtained by rotating and flipping an initial configuration. In presence of random process variation, any of them has equal opportunity to be selected as the optimal implementation for a specific FPGA chip. If each individual from a large number of FPGAs is applied with the optimal among all candidate configurations, the overall timing performance is evidently improved compared to applying a single configuration to those FPGAs. Furthermore, the technique of LE swapping makes faster one of two neighboring LEs occupied by critical paths, which guarantees an incremental timing performance improvement based on any optimized design. Twenty MCNC benchmark circuitsare placed and routed by VPR [12]. Statistical timing performance is obtained by Monte-Carlo simulation with FPGA process variation model. The experimental results demonstrate evident timing yield improvement. Compared to previous VAD works, the proposed method saves the effort of variation characterization and design time. / Although process variation is always stated as a side-effect, it still offers some opportunities for variation-based applications. The invention of physically unclonable function (PUF) enlightens the researchers to translate physical uniqueness to digital identification. In the third part of this thesis, a compact chip identification (ID) circuit on FPGA is presented. An array of ring oscillators is used to measure the process variation. The chip ID is calculated based on their relative speeds. The repeatability of chip ID generation is a common challenge for all kinds of implementations, particularly when variations in operating conditions such as supply voltage and temperature are taken into account. To address this issue, configurable ring oscillators together with an orthogonal (re-)initialization scheme is used to improve reliability. The implementation of the proposed design is tested on nine Xilinx Spartan-3e FPGA chips. The experimental results show that the new method significantly enhances reliability of ID generation and tolerance to environmental changes. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Yu, Haile. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references (leaves 125-137). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese. / Abstract --- p.ii / Acknowledgement --- p.vi / Publication List --- p.viii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Introduction to Process Variation --- p.1 / Chapter 1.2 --- Variation Compensation --- p.3 / Chapter 1.2.1 --- Post-silicon Tuning --- p.3 / Chapter 1.2.2 --- Variation-Aware Design (VAD) --- p.5 / Chapter 1.3 --- Background and Prior Art --- p.6 / Chapter 1.3.1 --- Variation Characterization --- p.6 / Chapter 1.3.2 --- Variation Compensation --- p.8 / Chapter 1.3.3 --- Chip Identification --- p.11 / Chapter 1.4 --- Motivations --- p.17 / Chapter 1.4.1 --- Variation Characterization --- p.17 / Chapter 1.4.2 --- Timing Yield Improvement by Architectural Symmetry --- p.18 / Chapter 1.4.3 --- Chip Identification --- p.18 / Chapter 1.5 --- Key Contributions --- p.19 / Chapter 1.5.1 --- Variation Characterization --- p.19 / Chapter 1.5.2 --- Timing Yield Improvement by Architectural Symmetry --- p.20 / Chapter 1.5.3 --- Chip Identification --- p.20 / Chapter 1.6 --- Thesis Outline --- p.22 / Chapter 2 --- Variation Characterization for FPGA --- p.24 / Chapter 2.1 --- Introduction --- p.25 / Chapter 2.2 --- Characterization Primitives --- p.27 / Chapter 2.3 --- Methodology --- p.28 / Chapter 2.3.1 --- LE Characterization --- p.30 / Chapter 2.3.2 --- LUT Full Characterization --- p.33 / Chapter 2.3.3 --- Interconnect Characterization --- p.36 / Chapter 2.4 --- Implementation --- p.39 / Chapter 2.5 --- Experimental Results --- p.41 / Chapter 2.5.1 --- Scaling Factor --- p.41 / Chapter 2.5.2 --- Characterization Results --- p.42 / Chapter 2.5.3 --- Verification --- p.47 / Chapter 2.6 --- Conclusion and Discussion --- p.49 / Chapter 2.6.1 --- Discussion --- p.50 / Chapter 3 --- Timing Yield Improvement for FPGA --- p.51 / Chapter 3.1 --- Introduction --- p.52 / Chapter 3.2 --- Variation Model --- p.52 / Chapter 3.2.1 --- Random Variation --- p.53 / Chapter 3.2.2 --- Spatial Correlation --- p.54 / Chapter 3.3 --- Theoretical Analysis --- p.55 / Chapter 3.3.1 --- 1-out-of-N Redundancy Method --- p.55 / Chapter 3.3.2 --- Configuration-Level Redundancy vs. Fine-Grained Adjustment --- p.57 / Chapter 3.3.3 --- Coverage Rate of Fine-Grained Adjustment --- p.61 / Chapter 3.4 --- Architecture --- p.62 / Chapter 3.4.1 --- Modification for Configuration Rotation and Flip --- p.62 / Chapter 3.4.2 --- Modification for Fine-grained Adjustment --- p.65 / Chapter 3.5 --- Flow of Methodology --- p.66 / Chapter 3.6 --- Experimental Results --- p.68 / Chapter 3.7 --- Cost-Efficiency Comparison --- p.74 / Chapter 3.8 --- Conclusions --- p.76 / Chapter 4 --- Chip Identification Circuit for FPGA --- p.78 / Chapter 4.1 --- Introduction --- p.79 / Chapter 4.2 --- Design --- p.80 / Chapter 4.2.1 --- Measurement Circuits --- p.80 / Chapter 4.2.2 --- “Cell“ Composition and One-bit Generation --- p.82 / Chapter 4.3 --- Results --- p.85 / Chapter 4.3.1 --- Distribution of R[subscript i] --- p.86 / Chapter 4.3.2 --- Effect of P,T,N --- p.87 / Chapter 4.3.3 --- Distribution of 1’s and 0’s --- p.88 / Chapter 4.3.4 --- Hamming Distance --- p.89 / Chapter 4.3.5 --- Execution Time --- p.89 / Chapter 4.3.6 --- Variation with Temperature --- p.90 / Chapter 4.4 --- Conclusions --- p.93 / Chapter 5 --- Enhanced Chip Identification Circuit for FPGA --- p.96 / Chapter 5.1 --- Introduction --- p.96 / Chapter 5.2 --- Sources of Instability --- p.97 / Chapter 5.3 --- Implementation --- p.98 / Chapter 5.3.1 --- Overlapped Cell Composition --- p.98 / Chapter 5.3.2 --- Configurable RO --- p.99 / Chapter 5.3.3 --- Configuration Initialization --- p.101 / Chapter 5.3.4 --- Flow of Chip ID Generation --- p.107 / Chapter 5.4 --- Results --- p.109 / Chapter 5.4.1 --- Summary of Hardware Resource Consumption --- p.109 / Chapter 5.4.2 --- Statistical Analysis --- p.109 / Chapter 5.4.3 --- Environmental Influences --- p.117 / Chapter 5.5 --- Conclusion --- p.119 / Chapter 6 --- Conclusion --- p.120 / Chapter 6.1 --- Future Work --- p.122 / Chapter 6.1.1 --- Variation Characterization for FPGA --- p.122 / Chapter 6.1.2 --- Timing Yield Improvement for FPGA --- p.123 / Chapter 6.1.3 --- Chip Identification Circuit for FPGA --- p.124 / Bibliography --- p.137

This thesis examines the problem of reducing reconfiguration time of an island-style FPGA at its configuration memory level. The approach followed is to examine configuration encoding techniques in order to reduce the size of the bitstream that must be loaded onto the device to perform a reconfiguration. A detailed analysis of a set of benchmark circuits on various island-style FPGAs shows that a typical circuit randomly changes a small number of bits in the {\it null} or default configuration state of the device. This feature is exploited by developing efficient encoding schemes for configuration data. For a wide set of benchmark circuits on various FPGAs, it is shown that the proposed methods outperform all previous configuration compression methods and, depending upon the relative size of the circuit to the device, compress within 5\% of the fundamental information theoretic limit. Moreover, it is shown that the corresponding decoders are simple to implement in hardware and scale well with device size and available configuration bandwidth. It is not unreasonable to expect that with little modification to existing FPGA configuration memory systems and acceptable increase in configuration power a 10-fold improvement in configuration delay could be achieved. The main contribution of this thesis is that it defines the limit of configuration compression for the FPGAs under consideration and develops practical methods of overcoming this reconfiguration bottleneck. The functional density of reconfigurable devices could thereby be enhanced and the range of potential applications reasonably expanded.

Thesis (M.S.)--State University of New York at Binghamton, Electrical Engineering Dept., 2006. / Includes bibliographical references.

Modular Multiplication is a time-consuming arithmetic operation because it involves multiplication as well as division. Modular exponentiation can be performed as a sequence of modular multiplications. Speeding the modular multiplication increases the speed of modular exponentiation. Modular exponentiation and modular multiplication are heavily used in current cryptographic systems. Well-known cryptographic algorithms, such as RSA and Diffie-Hellman key exchange, require modular exponentiation operations. Elliptic curve cryptography (ECC) needs modular multiplication. Information security is increasingly becoming very important. Encryption and Decryption are very likely to be in many systems that exchange information to secure, verify, or authenticate data. Many systems, like the Internet, cellular phones, hand-held devices, and E-commerce, involve private and important information exchange and they need cryptography to make it secure. There are three possible solutions to accomplish the cryptographic computation: software, hardware using application-specific integrated circuits (ASICs), and hardware using field-programmable gate arrays (FPGAs). The software solution is the cheapest and most flexible one. But, it is the slowest. The ASIC solution is the fastest. But, it is inflexible, very expensive, and needs long development time. The FPGA solution is flexible, reasonably fast, and needs shorter development time. Montgomery multiplication algorithm is a very smart and efficient algorithm for calculating the modular multiplication. It replaces the division by a shift and modulus-addition (if needed) operations, which are much faster than regular division. The algorithm is also very suitable for a hardware implementation. Many designs have been proposed for fixed precision operands. A word-based algorithm and the scalable Montgomery multiplier based on this algorithm have been proposed later. The scalable multiplier can be configured to meet the design area-time tradeoff. Also, it can work for any operand precision up to the memory capacity. In this thesis, we develop a prototyping environment that can be used to verify the functionality of the scalable Montgomery multiplier on the circuit level. All the software, hardware, and firmware components of this environment will be described. Also, we will discuss how this environment can be used to develop cryptographic applications or test procedures on top of it. We also present two FPGA designs of the processing unit of the scalable Montgomery multiplier. The FPGA design techniques that have been used to optimize these designs are described. The implementation results are analyzed and the designs are compared against each other. The FPGA implementation of the first design is also compared against its ASIC implementation. / Graduation date: 2003