A comunicação entre circuitos integrados tem evoluído em desempenho e confiabilidade ao longo dos anos. Inicialmente os projetos utilizavam barramentos paralelos, onde existe a necessidade de uma grande quantidade de vias, utilizando muitos pinos de entrada e saída dos circuitos integrados resultando também em uma grande suscetibilidade a interferências eletromagnéticas (EMI) e descargas eletrostáticas (ESD). Na sequência, ficou claro que o modelo de barramento serial possuía ampla vantagem em relação ao predecessor, uma vez que este utiliza um menor número de vias, facilitando o processo de leiaute de placas, facilitando também a integridade de sinais possibilitando velocidades muito maiores apesar do menor número de vias. Este trabalho faz uma comparação entre os principais protocolos seriais de baixa e média velocidade. Nessa pesquisa, foram salientadas as características positivas e negativas de cada protocolo, e como resultado o enquadramento de cada um dos protocolos em um segmento de atuação mais apropriado. O objetivo deste trabalho é utilizar o resultado da análise comparativa dos protocolos seriais para propor um aparato de hardware capaz de suprir uma deficiência encontrada no protocolo serial I2C, amplamente utilizado na indústria, mas que possui restrições quando a aplicação necessita alta confiabilidade. O aparato, aqui chamado de Monitor de Barramento I2C, é capaz de verificar a integridade de dados, sinalizar métricas sobre a qualidade das comunicações, detectar falhas transitórias e erros permanentes no barramento e agir sobre os dispositivos conectados ao barramento para a recuperação de tais erros, evitando falhas. Foi desenvolvido um mecanismo de injeção de falhas para simular as falhas em dispositivos conectados ao barramento e, portanto, verificar a resposta do monitor. Resultados no PSoC5, da empresa Cypress, mostram que a solução proposta tem um baixo custo em termos de área e nenhum impacto no desempenho das comunicações. / The communication between integrated circuits has evolved in performance and reliability over the years. Initially projects used parallel buses, where there is a need for a large amount of wires, consuming many input and output pins of the integrated circuits resulting in a great susceptibility to electromagnetic interference (EMI) and electrostatic discharge (ESD). As a result, it became clear that the serial bus model had large advantage over predecessor, since it uses a smaller number of lanes, making the PCB layout process easier, which also facilitates the signal integrity allowing higher speeds despite fewer pathways. This work makes a comparison between the main low and medium speed serial protocols. The research has emphasized the positive and negative characteristics of each protocol, and as a result the framework of each of the protocols in a more appropriate market segment. The objective of this work is to use the results of comparative analysis of serial protocols to propose a hardware apparatus capable of filling a gap found in the I2C protocol, widely used in industry, but with limitations when the application requires high reliability. The apparatus, here called I2C Bus Monitor, is able to perform data integrity verification activities, to signalize metrics about the quality of communications, to detect transient faults and permanent errors on the bus and to act on the devices connected to the bus for the recovery of such errors avoiding failures. It was developed a fault injection mechanism to simulate faults in the devices connected to the bus and thus verify the monitor response. Results in the APSoC5 from Cypress show that the proposed solution has an extremely low cost overhead in terms of area and no performance impact in the communication.

Real time detection of Volatile Organic Compounds (VOCs) using Selected Ion Flow Tube – Mass Spectrometry (SIFT-MS) provides a unique opportunity for research into breath testing for clinical diagnosis. However, before engaging in research into breath analytes as markers of disease, appropriate breath collection methods are required. Collection of breath for SIFT-MS instruments fall into two categories, direct breath collection into the instrument and the remote breath collection onto a storage medium. This thesis describes the development and validation of both methods of breath collection equipment for SIFT-MS analysis. Development of the direct breath collection device involved standardising and optimising the way in which breath is sampled by SIFT-MS. Design considerations include ergonomics, patient safety, breathing resistance, materials, and appropriate operating conditions of the device. Results from materials testing showed that all materials emit VOCs and the best approach is to minimise VOC emission by careful material selection. To minimise flow resistance experienced by the patient, the capillary from which the SIFT-MS instrument samples, is placed as close as possible to the users mouth. The optimal operating temperature of the device was found to be 100°C - 120°C, which ensures that water vapour will not condense inside the capillary causing blockage. In order to ensure patient safety the device is adequately insulated using stagnant air which also minimises VOC emission from insulation materials. Because a SIFT-MS instrument is large and cannot be easily shifted around a hospital, a system of remote sample collection is required. It is also important to separately collect and analyse breath from the respiratory alveolar region. For this reason the remote breath collection device designed also fractionates collected breath samples into the breath from the upper airways and alveolar breath. The storage medium chosen for the collected breath samples is a gas sampling bag made from Tedlar™. Collection of breath into Tedlar™ bags allows breath to be stored as a whole air sample, the ideal form for analysis with the SIFT-MS technique. Alveolar breath is fractionated from deadspace gasses by measuring a subject's exhalation and collecting the portion of interest. The breath exhalation is measured by an averaging Pitot tube and pressure transducer. Signal processing and automation of the remote breath collection device is controlled by a Cypress Microsystems PSoC microcontroller. To validate the device isoprene and acetone concentrations in fractionated breath samples were compared with a whole breath sample. Results showed that the alveolar breath fraction had a higher concentration of acetone than the upper airway fraction, indicating that the breath was successfully fractioned. However, isoprene concentrations were lower in both fractions due to hyperventilation of the subject causing a dilution effect of alveolar VOCs. Therefore, a higher sample collection volume is required per exhalation, and regulating subjects' breathing rate will avoid the dilution effect observed in collected breath samples. Overall, this thesis had designed, developed and validated two forms of breath collection systems for use with SIFT-MS technology.

A comunicação entre circuitos integrados tem evoluído em desempenho e confiabilidade ao longo dos anos. Inicialmente os projetos utilizavam barramentos paralelos, onde existe a necessidade de uma grande quantidade de vias, utilizando muitos pinos de entrada e saída dos circuitos integrados resultando também em uma grande suscetibilidade a interferências eletromagnéticas (EMI) e descargas eletrostáticas (ESD). Na sequência, ficou claro que o modelo de barramento serial possuía ampla vantagem em relação ao predecessor, uma vez que este utiliza um menor número de vias, facilitando o processo de leiaute de placas, facilitando também a integridade de sinais possibilitando velocidades muito maiores apesar do menor número de vias. Este trabalho faz uma comparação entre os principais protocolos seriais de baixa e média velocidade. Nessa pesquisa, foram salientadas as características positivas e negativas de cada protocolo, e como resultado o enquadramento de cada um dos protocolos em um segmento de atuação mais apropriado. O objetivo deste trabalho é utilizar o resultado da análise comparativa dos protocolos seriais para propor um aparato de hardware capaz de suprir uma deficiência encontrada no protocolo serial I2C, amplamente utilizado na indústria, mas que possui restrições quando a aplicação necessita alta confiabilidade. O aparato, aqui chamado de Monitor de Barramento I2C, é capaz de verificar a integridade de dados, sinalizar métricas sobre a qualidade das comunicações, detectar falhas transitórias e erros permanentes no barramento e agir sobre os dispositivos conectados ao barramento para a recuperação de tais erros, evitando falhas. Foi desenvolvido um mecanismo de injeção de falhas para simular as falhas em dispositivos conectados ao barramento e, portanto, verificar a resposta do monitor. Resultados no PSoC5, da empresa Cypress, mostram que a solução proposta tem um baixo custo em termos de área e nenhum impacto no desempenho das comunicações. / The communication between integrated circuits has evolved in performance and reliability over the years. Initially projects used parallel buses, where there is a need for a large amount of wires, consuming many input and output pins of the integrated circuits resulting in a great susceptibility to electromagnetic interference (EMI) and electrostatic discharge (ESD). As a result, it became clear that the serial bus model had large advantage over predecessor, since it uses a smaller number of lanes, making the PCB layout process easier, which also facilitates the signal integrity allowing higher speeds despite fewer pathways. This work makes a comparison between the main low and medium speed serial protocols. The research has emphasized the positive and negative characteristics of each protocol, and as a result the framework of each of the protocols in a more appropriate market segment. The objective of this work is to use the results of comparative analysis of serial protocols to propose a hardware apparatus capable of filling a gap found in the I2C protocol, widely used in industry, but with limitations when the application requires high reliability. The apparatus, here called I2C Bus Monitor, is able to perform data integrity verification activities, to signalize metrics about the quality of communications, to detect transient faults and permanent errors on the bus and to act on the devices connected to the bus for the recovery of such errors avoiding failures. It was developed a fault injection mechanism to simulate faults in the devices connected to the bus and thus verify the monitor response. Results in the APSoC5 from Cypress show that the proposed solution has an extremely low cost overhead in terms of area and no performance impact in the communication.

A comunicação entre circuitos integrados tem evoluído em desempenho e confiabilidade ao longo dos anos. Inicialmente os projetos utilizavam barramentos paralelos, onde existe a necessidade de uma grande quantidade de vias, utilizando muitos pinos de entrada e saída dos circuitos integrados resultando também em uma grande suscetibilidade a interferências eletromagnéticas (EMI) e descargas eletrostáticas (ESD). Na sequência, ficou claro que o modelo de barramento serial possuía ampla vantagem em relação ao predecessor, uma vez que este utiliza um menor número de vias, facilitando o processo de leiaute de placas, facilitando também a integridade de sinais possibilitando velocidades muito maiores apesar do menor número de vias. Este trabalho faz uma comparação entre os principais protocolos seriais de baixa e média velocidade. Nessa pesquisa, foram salientadas as características positivas e negativas de cada protocolo, e como resultado o enquadramento de cada um dos protocolos em um segmento de atuação mais apropriado. O objetivo deste trabalho é utilizar o resultado da análise comparativa dos protocolos seriais para propor um aparato de hardware capaz de suprir uma deficiência encontrada no protocolo serial I2C, amplamente utilizado na indústria, mas que possui restrições quando a aplicação necessita alta confiabilidade. O aparato, aqui chamado de Monitor de Barramento I2C, é capaz de verificar a integridade de dados, sinalizar métricas sobre a qualidade das comunicações, detectar falhas transitórias e erros permanentes no barramento e agir sobre os dispositivos conectados ao barramento para a recuperação de tais erros, evitando falhas. Foi desenvolvido um mecanismo de injeção de falhas para simular as falhas em dispositivos conectados ao barramento e, portanto, verificar a resposta do monitor. Resultados no PSoC5, da empresa Cypress, mostram que a solução proposta tem um baixo custo em termos de área e nenhum impacto no desempenho das comunicações. / The communication between integrated circuits has evolved in performance and reliability over the years. Initially projects used parallel buses, where there is a need for a large amount of wires, consuming many input and output pins of the integrated circuits resulting in a great susceptibility to electromagnetic interference (EMI) and electrostatic discharge (ESD). As a result, it became clear that the serial bus model had large advantage over predecessor, since it uses a smaller number of lanes, making the PCB layout process easier, which also facilitates the signal integrity allowing higher speeds despite fewer pathways. This work makes a comparison between the main low and medium speed serial protocols. The research has emphasized the positive and negative characteristics of each protocol, and as a result the framework of each of the protocols in a more appropriate market segment. The objective of this work is to use the results of comparative analysis of serial protocols to propose a hardware apparatus capable of filling a gap found in the I2C protocol, widely used in industry, but with limitations when the application requires high reliability. The apparatus, here called I2C Bus Monitor, is able to perform data integrity verification activities, to signalize metrics about the quality of communications, to detect transient faults and permanent errors on the bus and to act on the devices connected to the bus for the recovery of such errors avoiding failures. It was developed a fault injection mechanism to simulate faults in the devices connected to the bus and thus verify the monitor response. Results in the APSoC5 from Cypress show that the proposed solution has an extremely low cost overhead in terms of area and no performance impact in the communication.

This Master’s thesis deals with the issue of lead-acid batteries, which are used in hybrid electric vehicles. The lead-acid batteries works in mode PSoC. In this mode occurs to degradation mechanisms at negative electrodes. These degradation mechanisms reduce the battery life. The practical part of Master’s thesis describes the production and a compilation of experimental cells and experimental part examines the characteristics of lead-acid batteries with the pressure to the electrode system.

Power management solutions such as voltage regulator (VR) mandate DC-DC converters with high power density, high switching frequency and high efficiency to meet the needs of future computers and telecom equipment. The trend towards DC-DC converters with higher switching frequency presents significant challenges to power MOSFET technology. Optimization of the MOSFETs plays an important role in improving low-voltage DC-DC converter performance. This dissertation focuses on developing and optimizing high performance low voltage power MOSFETs for high frequency applications. With an inherently large gate charge, the trench MOSFET suffers significant switching power losses and cannot continue to provide sufficient performance in high frequency applications. Moreover, the influence of parasitic impedance introduced by device packaging and PCB assembly in board level power supply designs becomes more pronounced as the output voltage continues to decrease and the nominal current continues to increase. This eventually raises the need for highly integrated solutions such as power supply in package (PSiP) or on chip (PSoC). However, it is often more desirable in some PSiP architectures to reverse the source/drain electrodes from electrical and/or thermal point of view. In this dissertation, a stacked-die Power Block PSiP architecture is first introduced to enable DC-DC buck converters with a current rating up to 40 A and a switching frequency in the MHz range. New high- and low-side NexFETs are specially designed and optimized for the new PSiP architecture to maximize its efficiency and power density. In particular, a new NexFET structure with iv its source electrode on the bottom side of the die (source-down) is designed to enable the innovative stacked-die PSiP technology with significantly reduced parasitic inductance and package footprint. It is also observed that in synchronous buck converter very fast switching of power MOSFETs sometimes leads to high voltage oscillations at the phase node of the buck converter, which may introduce additional power loss and cause EMI related problems and undesirable electrical stress to the power MOSFET. At the same time, the synchronous MOSFET plays an important role in determining the performance of the synchronous buck converter. The reverse recovery of its body diode and the Cdv/dt induced false trigger-on are two major mechanisms that impact the performance of the SyncFET. This dissertation introduces a new approach to effectively overcome the aforementioned challenges associated with the state-of-art technology. The threshold voltage of the low-side NexFET is intentionally reduced to minimize the conduction and body diode related power losses. Meanwhile, a monolithically integrated gate voltage pull-down circuitry is proposed to overcome the possible Cdv/dt induced turn-on issue inadvertently induced by the low VTH SynFET. Through extensive modeling and simulation, all these innovative concepts are integrated together in a power module and fabricated with a 0.35µm process. With all these novel device technology improvements, the new power module delivers a significant improvement in efficiency and offers an excellent solution for future high frequency, high current density DC-DC converters. Megahertz operation of a Power v Block incorporating these new device techniques is demonstrated with an excellent efficiency observed.

The popularity and demand for safe autonomous vehicles are on the rise. Advances in semiconductor technology have led to the integration of a wide range of sensors with high-performance computers, all onboard the autonomous vehicles. The complexity of the software controlling the vehicles has also seen steady growth in recent years. Verifying the control software using traditional verification techniques is difficult and thus increases their safety concerns. Runtime verification is an efficient technique to ensure the autonomous vehicle's actions are limited to a set of acceptable behaviors that are deemed safe. The acceptable behaviors are formally described in linear temporal logic (LTL) specifications. The sensor data is actively monitored to verify its adherence to the LTL specifications using monitors. Corrective action is taken if a violation of a specification is found. An unmanned aerial vehicle (UAV) development platform is proposed for the validation of monitors on configurable hardware. A high-fidelity simulator is used to emulate the UAV and the virtual environment, thereby eliminating the need for a real UAV. The platform interfaces the emulated UAV with monitors implemented on configurable hardware and autopilot software running on a flight controller. The proposed platform allows the implementation of monitors in an isolated and scalable manner. Scenarios violating the LTL specifications can be generated in the simulator to validate the functioning of the monitors. / Master of Science / Safety is one of the most crucial factors considered when designing an autonomous vehicle. Modern vehicles that use a machine learning-based control algorithm can have unpredictable behavior in real-world scenarios that were not anticipated while training the algorithm. Verifying the underlying software code with all possible scenarios is a difficult task. Runtime verification is an efficient solution where a relatively simple set of monitors validate the decisions made by the sophisticated control software against a set of predefined rules. If the monitors detect an erroneous behavior, they initiate a predetermined corrective action. Unmanned aerial vehicles (UAVs), like drones, are a class of autonomous vehicles that use complex software to control their flight. This thesis proposes a platform that allows the development and validation of monitors for UAVs using configurable hardware. The UAV is emulated on a high-fidelity simulator, thereby eliminating the time-consuming process of flying and validating monitors on a real UAV. The platform supports the implementation of multiple monitors that can execute in parallel. Scenarios to violate rules and cause the monitors to trigger corrective actions can easily be generated on the simulator.

This thesis deals with issues of the issue lead-acid batteries and their application in mode of hybrid electric vehicle. The experiment is focused on the production of electrodes to determine the effect five types of additives in negative active mass in PsoC(Partial State of Charge) mode. This simulates conditions occurring in the mode of hybrid electric vehicles (HEV).

Made available in DSpace on 2014-06-11T19:22:31Z (GMT). No. of bitstreams: 0 Previous issue date: 2008-05-30Bitstream added on 2014-06-13T20:47:51Z : No. of bitstreams: 1 freitas_rlb_me_ilha.pdf: 2701208 bytes, checksum: 5ab311e644d8a3837fea549fd3136b7e (MD5) / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) / Neste trabalho, descreve-se um sistema eletrônico informatizado implementado com o objetivo de medir a distribuição do peso corporal na região plantar de pacientes, visando relacioná-la diretamente à tipologia e deformidades dos pés e associando-a, indiretamente, a eventuais deformidades dos membros inferiores, coluna vertebral, algias músculoesqueléticas e instabilidades da postura humana. O sistema é constituído por células de carga com extensômetros, montadas em uma base metálica, circuito de condicionamento de sinais, circuito de interfaceamento e um display de cristal líquido. Foi construída uma plataforma piloto com 4 células de carga, mas o projeto do sistema prevê a construção de duas plataformas com 45 células de cargas, cada uma. As células de carga apresentaram resposta linear, precisão superior a 2%, resolução inferior a 0,5 N e histerese desprezível. São apresentados os resultados de medições, efetuadas com o sistema, para medir a distribuição de forças nas quatro células de carga, quando se aplicou sobre elas um peso conhecido. As informações foram apresentadas em um display de cristal líquido e posteriormente serão apresentadas na tela de um computador, por meio de um programa desenvolvido em Delphi, facilitando a visualização para especialistas da área, principalmente médicos, fisioterapeutas e terapeutas ocupacionais. Com o equipamento proposto será possível investigar, clinicamente, patologias estudadas pela Podologia, Posturologia e Podoposturologia, viabilizando, com as informações captadas pelo sistema, metodologias mais adequadas de tratamentos. / In this work we describe an electrical system implemented with the purpose of measuring the distribution of body weight in plantar region of patients, aiming to relate it directly to the typology and deformities of the feet and involving it, indirectly, to any deformities of the lower limbs, skeletal spine, muscle-skeletal pains and human posture instability. The system consists of load cells with strain gages within a metal base, signal conditioning circuit, interfacing circuit, and a liquid crystal display. A prototype platform with 4 load cells was built, but the system will have two platforms with 45 loads of cells, each one. The load cells presented linear response, precision better than 2%, resolution less than 0.5 N, and low hysteresis. We show the results of the force distribution when a know weight is applied over the four load cells. The informations have been presented in a liquid crystal display, but later they will be presented in the screen of a computer, facilitating the visualization for specialists, mainly doctors, physiotherapists and occupational therapists. With the proposed equipment it will be possible to investigate, clinically, pathologies studied by Podology, Posturology and Podoposturology making feasible, with the information obtained with the system, more appropriate methodologies of treatment.

Orientador: Aparecido Augusto de Carvalho / Banca: Nobuo Oki / Banca: Josivaldo Godoy da Silva / Resumo: Neste trabalho, descreve-se um sistema eletrônico informatizado implementado com o objetivo de medir a distribuição do peso corporal na região plantar de pacientes, visando relacioná-la diretamente à tipologia e deformidades dos pés e associando-a, indiretamente, a eventuais deformidades dos membros inferiores, coluna vertebral, algias músculoesqueléticas e instabilidades da postura humana. O sistema é constituído por células de carga com extensômetros, montadas em uma base metálica, circuito de condicionamento de sinais, circuito de interfaceamento e um display de cristal líquido. Foi construída uma plataforma piloto com 4 células de carga, mas o projeto do sistema prevê a construção de duas plataformas com 45 células de cargas, cada uma. As células de carga apresentaram resposta linear, precisão superior a 2%, resolução inferior a 0,5 N e histerese desprezível. São apresentados os resultados de medições, efetuadas com o sistema, para medir a distribuição de forças nas quatro células de carga, quando se aplicou sobre elas um peso conhecido. As informações foram apresentadas em um display de cristal líquido e posteriormente serão apresentadas na tela de um computador, por meio de um programa desenvolvido em Delphi, facilitando a visualização para especialistas da área, principalmente médicos, fisioterapeutas e terapeutas ocupacionais. Com o equipamento proposto será possível investigar, clinicamente, patologias estudadas pela Podologia, Posturologia e Podoposturologia, viabilizando, com as informações captadas pelo sistema, metodologias mais adequadas de tratamentos. / Abstract: In this work we describe an electrical system implemented with the purpose of measuring the distribution of body weight in plantar region of patients, aiming to relate it directly to the typology and deformities of the feet and involving it, indirectly, to any deformities of the lower limbs, skeletal spine, muscle-skeletal pains and human posture instability. The system consists of load cells with strain gages within a metal base, signal conditioning circuit, interfacing circuit, and a liquid crystal display. A prototype platform with 4 load cells was built, but the system will have two platforms with 45 loads of cells, each one. The load cells presented linear response, precision better than 2%, resolution less than 0.5 N, and low hysteresis. We show the results of the force distribution when a know weight is applied over the four load cells. The informations have been presented in a liquid crystal display, but later they will be presented in the screen of a computer, facilitating the visualization for specialists, mainly doctors, physiotherapists and occupational therapists. With the proposed equipment it will be possible to investigate, clinically, pathologies studied by Podology, Posturology and Podoposturology making feasible, with the information obtained with the system, more appropriate methodologies of treatment. / Mestre