Software defined radios (SDRs) have changed the paradigm of slowly designing custom radios, instead allowing designers to quickly iterate designs with a large range of functionality. With the help of environments like the open-source project, GNU Radio, a designer can prototype radios with greatly improved productivity. Unfortunately, due to software performance limitations, there is no way to achieve the range of radio designs made possible with actual physical radio hardware. In order for SDRs to become more prevalent in radio prototyping and development, accelerators must be added to high-throughput and computationally intensive portions. Custom DSPs, GPUs, and FPGAs have all been added to SDRs to try and expand their computational capabilities. One difficulty in this is that by adding these accelerators, the "instant gratification" dynamic of the GNU Radio is lost. In this thesis, an enhanced GNU Radio flow is presented that seamlessly augments the GNU Radio software-only model with FPGAs, yet preserves the GNU Radio dynamics by providing full-custom radio hardware/software structures in seconds. By delegating portions of a GNU Radio flow graph to networked FPGAs, a larger class of software-defined radios can be implemented. Assembly of the signal processing structures within the FPGAs is accomplished using an enhanced flow where modules are customized, placed, and routed in a fraction of the time required by the vendor tools. With rapid FPGA assembly, a GNU Radio designer retains the ability to perform "what-if" experiments, which in turn greatly enhances productivity. Due to the modular nature of GNU Radio and of the FPGA designs, a modular assembly of the FPGA hardware is used. In the flow presented here, optimized hardware library components are designed by a domain expert, and stored as compact placed-and-routed modules. When a designer requests the assembly of one or more components within a given FPGA via a GNU Radio Python script, the necessary library components are accessed and translated to an appropriate location within the chip. Then the ports of the modules are stitched together using a custom FPGA router. This process reduces the large compile times of hardware for an FPGA to reasonable software-like times. To the radio designer, the complexity of the underlying hardware is abstracted away, making it appear as if everything compiles and runs in software, allowing many iterations to be realized quickly. Radio design can continue at the speeds that GNU Radio designers are accustomed to but with the range of possible waveforms and general functionality extended. / Master of Science

Two research projects are proposed that rely on Tools for open Reconfigurable Computing (TORC) and the openness of the Xilinx tool chain. The first project, the Embedded FPGA Transmitter, relies on the ability to add arbitrary routes to a physical FPGA which serve no obvious purpose. These routes can then mimic an antenna and transmit directly from the FPGA. This mechanism is not supported utilizing standard hardware description languages; however, the Embedded FPGA Transmitter requires measurements on a real FPGA to determine success. The second project is a back-end tools accelerator designed to reduce the compilation time for FPGA times. As the complexity of FPGAs have exceeded over a million logic cells, the compilation problem size has greatly expanded. The open-source project, TORC, provides an excellent framework for new FPGA research that provides physical, real-world results to ensure the applicability of the research. / Master of Science