Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, December 2009. / Thesis Advisor(s): Fouts, Douglas J. ; Pace, Phillip E. "December 2009." Description based on title screen as viewed on January 27, 2010. Author(s) subject terms: Choi-Williams Distribution, Signal Processing, Algorithm Optimization, C programming, Low Probability of Intercept (LPI), Radar detection, Radar classification. Includes bibliographical references (p. 75-76). Also available in print.

Thesis (M.S. in Systems Engineering)--Naval Postgraduate School, September 2002. / Thesis advisor(s): Phillip E. Pace, Herschel H. Loomis. Includes bibliographical references (p. 159-160). Also available online.

Thesis (Ph.D.)--University of Texas at Arlington, 2009.

Thesis (Ph. D.)--Ohio State University, 2003. / Title from first page of PDF file. Document formatted into pages; contains xv, 162 p.: ill. (some col.). Includes abstract and vita. Advisor: Randolph L. Moses, Dept. of Electrical Engineering. Includes bibliographical references (p. 156-162).

Thesis (Ph.D.) -- University of Adelaide, Dept. of Electrical and Electronic Engineering, 2000. / Table of corrections inserted opposite table of contents. Bibliography: p.191-212.

Thesis (M.Eng.Sc.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 2002? / "August 2001." Includes bibliographical references (leaves 77-80).

Thesis (M.S.)--Rochester Institute of Technology, 2007. / Typescript. Includes bibliographical references (leaves 79-82).

<p>The aim of this pro ject was to evaluate the use of SIMD array architectures in radar </p><p>signal processing. This has been done by implementing one of the most demanding parts </p><p>of the radar signal processing chain for airborne radar on the CSX600 architecture devel- </p><p>oped by Clearspeed Technologies. The CSX600 architecture is a SIMD processor with 96 </p><p>processing elements which can be arranged either as a linera array or as a ring. The QR- </p><p>decomposition, which was the part chosen for implementation, is the most performance </p><p>demanding part of the STAP stage. In order to create a relevant test case the well known </p><p>RT STAP benchmark from Mitre Corporation has been used. Two different algorithms </p><p>for performing QR-decompositions have been implemented and verified. In both cases </p><p>it has been concluded that either longer (> </p><p>≈256) or shorter (< ≈32) processor array </p><p>lengths would, in general, yield a higher utilization ratio. The FLOP count and utiliza- </p><p>tion has been measured for both algorithms, and it has been concluded that at least eight </p><p>CSX600 processors are needed to meet the real-time demand of the benchmark.</p>

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No description available.