A popularidade da linguagem Java no mercado de sistemas embarcados está aumentando como uma alternativa à necessidade de compatibilidade de software e ao crescimento da complexidade das aplicações, notadamente em eletrônica de consumo e automação industrial, mercado que também está se expandindo. Apesar de um melhor gerenciamento da complexidade do software permitido pela linguagem Java, as restrições de necessidade de economia de energia, baixo consumo de potência e necessidade de desempenho impostas aos sistemas embarcados, com especial ênfase aos sistemas portáteis, são potencializadas. Entretanto, as características da Java Virtual Machine, baseada em uma máquina de pilha, abrem possibilidades de otimização do processamento de aplicações embarcadas inerentes às máquinas de pilha e ainda não devidamente exploradas pelos processadores Java atuais. Com a aplicação de tradução binária ao código Java e utilização de técnicas de reconfiguração, consegue-se obter aumento de performance com simultânea economia de energia, permitindo-se uma melhor adequação da execução das aplicações Java para o domínio dos sistemas embarcados. Este trabalho apresenta uma unidade reconfigurável de granularidade grossa, o Javarray, a ser acoplada a um processador de execução Java nativa, destinada à execução otimizada dos blocos básicos mais representativos das aplicações embarcadas Java. Dessa forma, conseguimos explorar ILP de uma maneira simples e com a reconfiguração de poucos blocos básicos obtivemos uma redução no número de instruções executadas em até 42%, aumentamos o desempenho das aplicações em até 2,6 vezes e obtivemos economias de energia de até 64%, ao mesmo tempo em que mantivemos compatibilidade de software com as aplicações Java, e em muitos casos obtivemos simultânea redução na potência consumida. Esses dados referem-se a um conjunto de 3 aplicações específicas utilizadas por nosso grupo. A topologia básica do Javarray é desenvolvida a partir da análise de profiles de aplicações embarcadas, a partir da qual algumas variações organizacionais são exploradas. Em especial, desenvolveu-se uma arquitetura seqüencial, que habilita a utilização de técnicas de pipeline no Javarray, permitindo a exploração de paralelismo de mais alto nível. Como produto secundário dos esforços pela busca de economia de energia através do aumento de desempenho – foco deste trabalho – apresenta-se então os primeiros estudos acerca da possibilidade de execução de processamento do tipo stream em um pipeline de instruções reconfiguráveis no Javarray, aumentando dessa forma o IPC e reduzindo o impacto do consumo estático de energia. / Althought with a better management of the softwares’ complexity, allowed by the Java language, the restrictions of energy saving, low power consumption and the need of performance imposed to the embedded systems, with special emphasis to the mobile systems, are potentialized The popularity of the Java language in the embedded systems market is increasing as an alternative to the software compatibility necessity and the applications’ complexity growth, notably at consumption electronic and industrial automation, market which is also expanding. However, the characteristics of Java Virtual Machine, based upon a stack machine, open new possibilities to the optimization of embedded systems processing inherent to the stack machines and not yet properly explored by the actual Java processors. With the exploitation of binary translation to the Java code and the use of reconfiguration techniques, we can improve the performance with simultaneous energy savings, achieving achieving a better fit of Java applications execution to the embedded systems domain. This work presents a coarse grain reconfigurable unit, the Javarray, to be coupled to a native execution Java microcontroller, designed to the optimized execution of the embedded systems applications more representative basic blocks. With this, we can explore ILP in a simple way and reduce the number of the executed instructions up to 42%, improving the performance up to 2.6 times and saving energy up to 64%, at the same time in which allowing for Java compatibility and, in many cases, still having less power consumption. This data refer to a set of 3 specific applications used by our research group. The basic Javarray topology is developed from the analysis of the embedded application profiles, form which some organizational variations are explored. In special, it was designed a sequential architecture, which enables the use of pipeline techniques on the Javarray, allowing for the exploitation of coarser grains parallelism. As a secondary product of the search for the energy savings through the performance speedup – focus of this work – it is presented the first studies about the possibility of stream-based processing execution in a pipeline of reconfigurable instructions on the Javarray, this way increasing the IPC and reducing the static energy consumption impact.

A complexidade dos sistemas embarcados está crescendo devido à agregação de funcionalidades em um único dispositivo eletrônico e a heterogeneidade de comportamento das aplicações que compõe estas funcionalidades agrava este cenário. Atualmente, os projetistas de processadores estão buscando outro paradigma de computação para ser empregado neste tipo de dispositivo. A aceleração da execução dos processadores Superescalares está estagnada, a extração do paralelismo no modelo Von- Neumann está chegando ao limite teórico. Arquiteturas Dataflow são uma possível solução para este problema, entretanto a área disponível em silício da tecnologia atual não comporta a implementação deste tipo de arquitetura. Arquiteturas reconfiguráveis aparecem como uma solução viável para a exploração de um alto nível de paralelismo, sendo factível a implementação deste tipo de arquitetura nas atuais tecnologias CMOS. Entretanto, a inserção do hardware reconfigurável ocasiona uma elevação na área ocupada e, conseqüentemente, na potência consumida. É neste cenário que este trabalho se insere. Uma arquitetura reconfigurável foi escolhida como estudo de caso, sendo acoplada a um processador MIPS R3000. Além disto, foi desenvolvida uma ferramenta que, automaticamente, constrói um hardware otimizado através da exploração de recursos necessários para obter o máximo grau de paralelismo da execução de um conjunto de aplicações. O acoplamento desta ferramenta com a técnica de tradução binária utilizada nesta arquitetura reconfigurável provê uma exploração estática/dinâmica. Estática pelo ponto de vista de construção de uma nova unidade reconfigurável otimizada em área antes da fabricação do chip. Dinâmica devido a adaptabilidade da execução do tradutor binário, após a fabricação da unidade otimizada gerada pela ferramenta, a unidade otimizada alcança as mesmas acelerações demonstradas na unidade não otimizada com uma menor área ocupada e potência consumida. Além disto, neste trabalho é demonstrado o impacto na potência consumida pelo sistema fornecido por uma técnica de desligamento de blocos da unidade funcional reconfigurável. Assim, as explorações da área e do consumo de potência demonstraram ser factível a inserção da arquitetura reconfigurável proposta em um dispositivo embarcado. / Nowadays, the large amount of complex and heterogeneous functionalities that are found on a single embedded device has driven designers to create novel solutions to increase the performance of embedded processors and, at the same time, maintain power dissipation as low as possible. While the instruction level parallelism exploitation is reaching the theoretical limit, Dataflow architectures are seen as a reasonable proposal to solve this problem. However, even for near future CMOS technologies, the price to pay for using such architectures is still too high. Reconfigurable architectures could be a possible solution to explore higher-levels of parallelism, and their deployment on current CMOS technologies is feasible. However, the fusion of a reconfigurable hardware with a general-purpose processor still implies in a high area overhead, besides the elevated power consumption. The proposal of this work is to couple static and dynamic techniques to achieve a low-power, high performance reconfigurable architecture that can show speed ups for several heterogeneous applications with the minimum possible area overhead. At design time, the static exploitation produces a new reconfigurable unit optimized in area. Thanks to the proposed dynamic reconfiguration mechanism, the optimized reconfigurable unit provides acceleration and low power dissipation, adapting to the different degrees of parallelism available in the application, and accelerating applications not foreseen at design time.

Switched-capacitor (SC) DC-DC converters provide a viable solution for on-chip DC-DC conversion as all the components required are available in most processes. However, power efficiency, power density characteristics of SC converters are adversely affected by the integration, and characteristics such as response time and noise can be further improved with an on-chip converter. An analysis on speed, power efficiency, and noise performance of SC converters is presented and verified using simulations. Based on the analysis two techniques, converter-gating and adaptive gain control, are developed. Converter-gating uses a combination of smaller stages and reconfiguration during transient load steps to improve the power efficiency and transient response speed. The stages of the converter are also distributed across the die to reduce the voltage drop and noise on power supply. Adaptive gain control improves transient response through manipulation of the gain of the integrator in the control loop. This technique focuses on improving the response time during converter reconfiguration and offers a general solution to transient response improvement instead of focusing on the worst case scenario which is usually the largest transient load step. The techniques developed are then implemented in ST 28nm FDSOI process and test methodologies are discussed.

Ant Colony Optimization (ACO) is a metaheuristic used to solve combinatorial optimization problems. As with other metaheuristics, like evolutionary methods, ACO algorithms often show good optimization behavior but are slow when compared to classical heuristics. Hence, there is a need to find fast implementations for ACO algorithms. In order to allow a fast parallel implementation, we propose several changes to a standard form of ACO algorithms. The main new features are the non-generational approach and the use of a threshold based decision function for the ants. We show that the new algorithm has a good optimization behavior and also allows a fast implementation on reconfigurable processor arrays. This is the first implementation of the ACO approach on a reconfigurable architecture. The running time of the algorithm is quasi-linear in the problem size n and the number of ants on a reconfigurable mesh with n2 processors, each provided with only a constant number of memory words.

Many digital logic applications can take advantage of the reconfiguration capability of Field Programmable Gate Arrays (FPGAs) to dynamically patch design flaws, recover from faults, or time-multiplex between functions. Partial reconfiguration is the process by which a user modifies one or more modules residing on the FPGA device independently of the others. Partial Reconfiguration reduces the granularity of reconfiguration to be a set of columns or rectangular region of the device. Decreasing the granularity of reconfiguration results in reduced configuration filesizes and, thus, reduced configuration times. When compared to one bitstream of a non-partial reconfiguration implementation, smaller modules resulting in smaller bitstream filesizes allow an FPGA to implement many more hardware configurations with greater speed under similar storage requirements. To realize the benefits of partial reconfiguration in a wider range of applications, this thesis begins with a survey of FPGA fault-handling methods, which are compared using performance-based metrics. Performance analysis of the Genetic Algorithm (GA) Offline Recovery method is investigated and candidate solutions provided by the GA are partitioned by age to improve its efficiency. Parameters of this aging technique are optimized to increase the occurrence rate of complete repairs. Continuing the discussion of partial reconfiguration, the thesis develops a case-study application that implements one partial reconfiguration module to demonstrate the functionality and benefits of time multiplexing and reveal the improved efficiencies of the latest large-capacity FPGA architectures. The number of active partial reconfiguration modules implemented on a single FPGA device is increased from one to eight to implement a dynamic video-processing architecture for Discrete Cosine Transform and Motion Estimation functions to demonstrate a 55-fold reduction in bitstream storage requirements thus improving partial reconfiguration capability.

Coarse-Grained Reconfigurable Architectures(CGRAs) can be employed for accelerating computational workloads that demand both flexibility and performance. CGRAs comprise a set of computation elements interconnected using a network and this interconnection of computation elements is referred to as a reconfigurable fabric. The size of application that can be accommodated on the reconfigurable fabric is limited by the size of instruction buffers associated with each Compute element. When an application cannot be accommodated entirely, application is partitioned such that each of these partitions can be executed on the reconfigurable fabric. These partitions are scheduled by an orchestrator. The orchestrator employs dynamic dataflow execution paradigm. Dynamic dataflow execution paradigm has inherent support for synchronization and helps in exploitation of parallelism that exists across application partitions. In this thesis, we present a compiler that targets such CGRAs. The compiler presented in this thesis is capable of accepting applications specified in C89 standard. To enable architectural design space exploration, the compiler is designed such that it can be customized for several instances of CGRAs employing dataflow execution paradigm at the orchestrator. This can be achieved by specifying the appropriate configuration parameters to the compiler. The focus of this thesis is to provide efficient support for various kinds of parallelism while ensuring correctness. The compiler is designed to support fine-grained task level parallelism that exists across iterations of loops and function calls. Additionally, compiler can also support pipeline parallelism, where a loop is split into multiple stages that execute in a pipelined manner. The prototype compiler, which targets multiple instances of a CGRA, is demonstrated in this thesis. We used this compiler to target multiple variants of CGRAs employing dataflow execution paradigm. We varied the reconfigur-able fabric, orchestration mechanism employed, size of instruction buffers. We also choose applications from two different domains viz. cryptography and linear algebra. The execution time of the CGRA (the best among all instances) is compared against an Intel Quad core processor. Cryptography applications show a performance improvement ranging from more than one order of magnitude to close to two orders of magnitude. These applications have large amounts of ILP and our compiler could successfully expose the ILP available in these applications. Further, the domain customization also played an important role in achieving good performance. We employed two custom functional units for accelerating Cryptography applications and compiler could efficiently use them. In linear algebra kernels we observe multiple iterations of the loop executing in parallel, effectively exploiting loop-level parallelism at runtime. Inspite of this we notice close to an order of magnitude performance degradation. The reason for this degradation can be attributed to the use of non-pipelined floating point units, and the delays involved in accessing memory. Pipeline parallelism was demonstrated using this compiler for FFT and QR factorization. Thus, the compiler is capable of efficiently supporting different kinds of parallelism and can support complete C89 standard. Further, the compiler can also support different instances of CGRAs employing dataflow execution paradigm.

Les avancées technologiques ont permis la commercialisation à grande échelle de terminaux mobiles. De ce fait, l’homme est de plus en plus connecté et partout. Ce nombre grandissant d’usagers du réseau ainsi que la forte croissance du contenu disponible, aussi bien d’un point de vue quantitatif que qualitatif saturent les réseaux et l’augmentation des moyens matériels (passage à la fibre optique) ne suffisent pas. Pour surmonter cela, les réseaux doivent prendre en compte le type de contenu (texte, vidéo, ...) ainsi que le contexte d’utilisation (état du réseau, capacité du terminal, ...) pour assurer une qualité d’expérience optimum. A ce sujet, la vidéo fait partie des contenus les plus critiques. Ce type de contenu est non seulement de plus en plus consommé par les utilisateurs mais est aussi l’un des plus contraignant en terme de ressources nécéssaires à sa distribution (taille serveur, bande passante, …). Adapter un contenu vidéo en fonction de l’état du réseau (ajuster son débit binaire à la bande passante) ou des capacités du terminal (s’assurer que le codec soit nativement supporté) est indispensable. Néanmoins, l’adaptation vidéo est un processus qui nécéssite beaucoup de ressources. Cela est antinomique à son utilisation à grande echelle dans les appareils à bas coûts qui constituent aujourd’hui une grande part dans l’ossature du réseau Internet. Cette thèse se concentre sur la conception d’un système d’adaptation vidéo à bas coût et temps réel qui prendrait place dans ces réseaux du futur. Après une analyse du contexte, un système d’adaptation générique est proposé et évalué en comparaison de l’état de l’art. Ce système est implémenté sur un FPGA afin d’assurer les performances (temps-réels) et la nécessité d’une solution à bas coût. Enfin, une étude sur les effets indirects de l’adaptation vidéo est menée. / On the one hand, technology advances have led to the expansion of the handheld devices market. Thanks to this expansion, people are more and more connected and more and more data are exchanged over the Internet. On the other hand, this huge amound of data imposes drastic constrains in order to achieve sufficient quality. The Internet is now showing its limits to assure such quality. To answer nowadays limitations, a next generation Internet is envisioned. This new network takes into account the content nature (video, audio, ...) and the context (network state, terminal capabilities ...) to better manage its own resources. To this extend, video manipulation is one of the key concept that is highlighted in this arising context. Video content is more and more consumed and at the same time requires more and more resources. Adapting videos to the network state (reducing its bitrate to match available bandwidth) or to the terminal capabilities (screen size, supported codecs, …) appears mandatory and is foreseen to take place in real time in networking devices such as home gateways. However, video adaptation is a resource intensive task and must be implemented using hardware accelerators to meet the desired low cost and real time constraints.In this thesis, content- and context-awareness is first analyzed to be considered at the network side. Secondly, a generic low cost video adaptation system is proposed and compared to existing solutions as a trade-off between system complexity and quality. Then, hardware conception is tackled as this system is implemented in an FPGA based architecture. Finally, this system is used to evaluate the indirect effects of video adaptation; energy consumption reduction is achieved at the terminal side by reducing video characteristics thus permitting an increased user experience for End-Users.

Redes de sensores sem fio (RSSFs) heterogêneas podem combinar nós estáticos e nós móveis. Os nós móveis podem ainda conter um hardware mais sofisticado quando comparado aos nós estáticos. Veículos aéreos não tripulados (VANTs) podem conferir mobilidade ao nó sensor aumentando a flexibilidade da RSSF onde ele está inserido. Tanto os VANTs quanto outros n´os sensores comuns podem conter uma arquitetura de hardware reconfiguraável, como por exemplo um FPGA, e com isso adquirir um poder computacional diferenciado. RSSFs propiciam um grande e interessante espectro de aplicações possíveis, tais como vigilância aérea, suporte `a segurança pública entre outros. As RSSFs podem ser configuradas através do uso de agentes móveis, que são capazes de migrar carregando as tarefas que serão executadas nos n´os. Neste cenário, este trabalho descreve uma arquitetura de agentes reconfiguráveis para redes de sensores sem fio. Os agentes são capazes de serem executados como um agente puramente em software, ou também como um agente em hardware, de- pendendo do ambiente de execução disponível e do design escolhido. A arquitetura proposta para o agente reconfiguraável apresenta a transparência necessária ao agente para que o resto do sistema não perceba a natureza dos agentes que estão sendo executados na plataforma. Além disso, a arquitetura permite a migração dinâmica de agentes que reconfiguram o sistema também de uma maneira transparente. São mostrados exemplos de casos de uso que demostram a viabilidade de uso da arquitetura proposta e este trabalho ainda mostra a análise realizada sobre estas plataformas. / Heterogeneous wireless sensor networks (WSN) can combine static nodes and mobile nodes. Theses mobile nodes may contain a sophisticated hardware when compared to static nodes. Unmanned aircraft vehicles (UAVs) can confer mobility to the sensor node increasing the flexibility of the WSN to where it is inserted. UAVs as well as other common sensor nodes can have a reconfigurable hardware architecture, as, for example, an FPGA and with this achieve a differentiated computational power. WSNs enable a vast and interesting spectrum of possible applications, like aerial surveillance, public security support, among others. The WSNs can be configured by the use of mobile agents, which are capable of migrating among the nodes, carrying the tasks to be executed and that will be instantiated on a given node. In this scenario, this work describes an architecture of reconfigurable agents to wireless sensor networks. The agents can be implemented purely in software or as a hardware agent, depending on the available execution environment and on the chosen design. The proposed architecture presents the necessary transparency to the agent so that the rest of the system is not aware of the nature of the agents that are implemented on the platform. Furthermore, the architecture enables dynamic migration of agents that reconfigure the system in a transparent way as well. In this work, use cases examples that demonstrate the feasibility of using the proposed architecture are shown, as well as the analysis performed on these platforms.

Redes de sensores sem fio (RSSFs) heterogêneas podem combinar nós estáticos e nós móveis. Os nós móveis podem ainda conter um hardware mais sofisticado quando comparado aos nós estáticos. Veículos aéreos não tripulados (VANTs) podem conferir mobilidade ao nó sensor aumentando a flexibilidade da RSSF onde ele está inserido. Tanto os VANTs quanto outros n´os sensores comuns podem conter uma arquitetura de hardware reconfiguraável, como por exemplo um FPGA, e com isso adquirir um poder computacional diferenciado. RSSFs propiciam um grande e interessante espectro de aplicações possíveis, tais como vigilância aérea, suporte `a segurança pública entre outros. As RSSFs podem ser configuradas através do uso de agentes móveis, que são capazes de migrar carregando as tarefas que serão executadas nos n´os. Neste cenário, este trabalho descreve uma arquitetura de agentes reconfiguráveis para redes de sensores sem fio. Os agentes são capazes de serem executados como um agente puramente em software, ou também como um agente em hardware, de- pendendo do ambiente de execução disponível e do design escolhido. A arquitetura proposta para o agente reconfiguraável apresenta a transparência necessária ao agente para que o resto do sistema não perceba a natureza dos agentes que estão sendo executados na plataforma. Além disso, a arquitetura permite a migração dinâmica de agentes que reconfiguram o sistema também de uma maneira transparente. São mostrados exemplos de casos de uso que demostram a viabilidade de uso da arquitetura proposta e este trabalho ainda mostra a análise realizada sobre estas plataformas. / Heterogeneous wireless sensor networks (WSN) can combine static nodes and mobile nodes. Theses mobile nodes may contain a sophisticated hardware when compared to static nodes. Unmanned aircraft vehicles (UAVs) can confer mobility to the sensor node increasing the flexibility of the WSN to where it is inserted. UAVs as well as other common sensor nodes can have a reconfigurable hardware architecture, as, for example, an FPGA and with this achieve a differentiated computational power. WSNs enable a vast and interesting spectrum of possible applications, like aerial surveillance, public security support, among others. The WSNs can be configured by the use of mobile agents, which are capable of migrating among the nodes, carrying the tasks to be executed and that will be instantiated on a given node. In this scenario, this work describes an architecture of reconfigurable agents to wireless sensor networks. The agents can be implemented purely in software or as a hardware agent, depending on the available execution environment and on the chosen design. The proposed architecture presents the necessary transparency to the agent so that the rest of the system is not aware of the nature of the agents that are implemented on the platform. Furthermore, the architecture enables dynamic migration of agents that reconfigure the system in a transparent way as well. In this work, use cases examples that demonstrate the feasibility of using the proposed architecture are shown, as well as the analysis performed on these platforms.

Redes de sensores sem fio (RSSFs) heterogêneas podem combinar nós estáticos e nós móveis. Os nós móveis podem ainda conter um hardware mais sofisticado quando comparado aos nós estáticos. Veículos aéreos não tripulados (VANTs) podem conferir mobilidade ao nó sensor aumentando a flexibilidade da RSSF onde ele está inserido. Tanto os VANTs quanto outros n´os sensores comuns podem conter uma arquitetura de hardware reconfiguraável, como por exemplo um FPGA, e com isso adquirir um poder computacional diferenciado. RSSFs propiciam um grande e interessante espectro de aplicações possíveis, tais como vigilância aérea, suporte `a segurança pública entre outros. As RSSFs podem ser configuradas através do uso de agentes móveis, que são capazes de migrar carregando as tarefas que serão executadas nos n´os. Neste cenário, este trabalho descreve uma arquitetura de agentes reconfiguráveis para redes de sensores sem fio. Os agentes são capazes de serem executados como um agente puramente em software, ou também como um agente em hardware, de- pendendo do ambiente de execução disponível e do design escolhido. A arquitetura proposta para o agente reconfiguraável apresenta a transparência necessária ao agente para que o resto do sistema não perceba a natureza dos agentes que estão sendo executados na plataforma. Além disso, a arquitetura permite a migração dinâmica de agentes que reconfiguram o sistema também de uma maneira transparente. São mostrados exemplos de casos de uso que demostram a viabilidade de uso da arquitetura proposta e este trabalho ainda mostra a análise realizada sobre estas plataformas. / Heterogeneous wireless sensor networks (WSN) can combine static nodes and mobile nodes. Theses mobile nodes may contain a sophisticated hardware when compared to static nodes. Unmanned aircraft vehicles (UAVs) can confer mobility to the sensor node increasing the flexibility of the WSN to where it is inserted. UAVs as well as other common sensor nodes can have a reconfigurable hardware architecture, as, for example, an FPGA and with this achieve a differentiated computational power. WSNs enable a vast and interesting spectrum of possible applications, like aerial surveillance, public security support, among others. The WSNs can be configured by the use of mobile agents, which are capable of migrating among the nodes, carrying the tasks to be executed and that will be instantiated on a given node. In this scenario, this work describes an architecture of reconfigurable agents to wireless sensor networks. The agents can be implemented purely in software or as a hardware agent, depending on the available execution environment and on the chosen design. The proposed architecture presents the necessary transparency to the agent so that the rest of the system is not aware of the nature of the agents that are implemented on the platform. Furthermore, the architecture enables dynamic migration of agents that reconfigure the system in a transparent way as well. In this work, use cases examples that demonstrate the feasibility of using the proposed architecture are shown, as well as the analysis performed on these platforms.