This study was conducted to determine whether or not combining feedback modes resulted in improved operator performance, given a specific task and environment. A common industrial handheld scanner with multiple feedback settings was used to assess four experimental feedback conditions (auditory, auditory-visual, auditory-tactile, and auditory-visual-tactile) during simulated box scanning tasks. Participants completed four-50 box trials in a single test session where boxes were scanned and located based on the feedback provided regarding the scan. Task completion time and ranks, hit rate and false alarms were recorded. While the auditory-visual-tactile feedback combination produced the fastest performance time, there was no statistically significant improvement in operator performance between the four feedback settings tested. By understanding the most important feedback modes, or combination of such, identification of the best scanner settings for this device and task can be made.

This research investigates alternate methods of implementing a redundant communications ring for polled network applications. FDDI and a unique solution (the tone method) designed specifically for this application are compared. In polled networks one of the most critical parameters is the time required to interrogate all of the nodes in the network. This parameter, called the poll time, is compared for the two solutions under various operating conditions, including the instances when the ring is intact and when the ring has experienced a failure, causing it to operate in the redundant mode. As expected, the solution designed specifically for this application performed better than FDDI. The tone method, which requires very little overhead and is not limited by distance or number of nodes, is described in detail, as are the results of poll time comparisons. / Master of Science

Published Article / This paper will discuss the final implementation of an Improved OPC data logging system and its improvements over the original. The improved solution focused on the hardware, software and administrative components of the system; taking the reliability and performance of each component into consideration. The software components include the database, the data acquisition and logging client application (DALC) and the various OPC servers; the hardware component includes the servers that will run the software components, power management and Redundant Array of Independents Disks (RAID) technologies; and the administrative component includes implementing automated routines to backup the important data and archive old logs.

Approved for public release; distribution is unlimited / The determination of a system's life distribution usually requires the synthesis of a mixture of system survival modes. In order to alleviate the normal non-trivial calculations, this paper presents the concept of a reliability shorthand. After describing the possible ways a system can survive a mission, the practitioner of this shorthand can use stock formulas to obtain a system's survival function. Then simple insertion of the failure rates of the system's components into the known equations results in the system's reliability. Simple examples show the convenience of this shorthand. The TI-59 is demonstrated to be a useful tool; adequate to implement the methodology. / http://archive.org/details/introductiontore00repi / Lieutenant Commander, United States Navy

Declarative process models define the behaviour of business processes as a set of constraints. Declarative process discovery aims at inferring such constraints from event logs. Existing discovery techniques verify the satisfaction of candidate constraints over the log, but completely neglect their interactions. As a result, the inferred constraints can be mutually contradicting and their interplay may lead to an inconsistent process model that does not accept any trace. In such a case, the output turns out to be unusable for enactment, simulation or verification purposes. In addition, the discovered model contains, in general, redundancies that are due to complex interactions of several constraints and that cannot be cured using existing pruning approaches. We address these problems by proposing a technique that automatically resolves conflicts within the discovered models and is more powerful than existing pruning techniques to eliminate redundancies. First, we formally define the problems of constraint redundancy and conflict resolution. Second, we introduce techniques based on the notion of automata-product monoid, which guarantees the consistency of the discovered models and, at the same time, keeps the most interesting constraints in the pruned set. The level of interestingness is dictated by user-specified prioritisation criteria. We evaluate the devised techniques on a set of real-world event logs.

We present a design technique, called partial evaluation triple modular redundancy for hardening combinational circuits against Single Event Upsets (SEU). The input environment is given in terms of signal probabilities of the lines. This is useful information to determine the redundant gates of the given circuit. The basic ideas of partial redundancy and temporal triple modular redundancy are used together to harden the circuit against SEUs. The concept of partial redundancy is used to eliminate the gates whose outputs can be determined in advance. This technique fails in cases when the actual inputs to the circuit are not in accordance to the rounded logic values. In such cases the technique of temporal TMR is used. However, there is some overhead in this process because of the voter circuits and the need to choose the outputs computed by partially evaluated circuit and circuit using temporal TMR. For testing the circuit exhaustively against SEUs, a fault insertion simulator is used. This simulator introduces errors in the circuits during simulation which represent SEUs. This technique of partial evaluation redundancy is thoroughly tested on MCNC’91 benchmarks using Cadence NCLaunch simulator. By employing this technique, in most of the cases we can reduce the area overhead of the hardened circuit when compared with the traditional Triple Modular Redundancy (TMR). The improvement in area is based on the total number of gates and the actual number of outputs. For circuits with large number of gates and less number of outputs, there is greater savings in area. In some cases, the area overhead because of the proposed technique is greater than the traditional TMR. This usually occurs in smaller circuits or in circuits with more number of outputs.

There is a growing demand for high-speed arithmetic co-processors for use in applications with computationally intensive tasks. For instance, Fast Fourier Transform (FFT) co-processors are used in real-time multimedia services and financial applications use decimal co-processors to perform large amounts of decimal computations. Using redundant number systems to eliminate word-wide carry propagation within interim operations is a well-known technique to increase the speed of arithmetic hardware units. Redundant number systems are mostly useful in applications where many consecutive arithmetic operations are performed prior to the final result, making it advantageous for arithmetic co-processors. This thesis discusses the implementation of two popular arithmetic co-processors based on redundant number systems: namely, the binary FFT co-processor and the decimal arithmetic co-processor. FFT co-processors consist of several consecutive multipliers and adders over complex numbers. FFT architectures are implemented based on fixed-point and floating-point arithmetic. The main advantage of floating-point over fixed-point arithmetic is the wide dynamic range it introduces. Moreover, it avoids numerical issues such as scaling and overflow/underflow concerns at the expense of higher cost. Furthermore, floating-point implementation allows for an FFT co-processor to collaborate with general purpose processors. This offloads computationally intensive tasks from the primary processor. The first part of this thesis, which is devoted to FFT co-processors, proposes a new FFT architecture that uses a new Binary-Signed Digit (BSD) carry-limited adder, a new floating-point BSD multiplier and a new floating-point BSD three-operand adder. Finally, a new unit labeled as Fused-Dot-Product-Add (FDPA) is designed to compute AB+CD+E over floating-point BSD operands. The second part of the thesis discusses decimal arithmetic operations implemented in hardware using redundant number systems. These operations are popularly used in decimal floating-point co-processors. A new signed-digit decimal adder is proposed along with a sequential decimal multiplier that uses redundant number systems to increase the operational frequency of the multiplier. New redundant decimal division and square-root units are also proposed. The architectures proposed in this thesis were all implemented using Hardware-Description-Language (Verilog) and synthesized using Synopsys Design Compiler. The evaluation results prove the speed improvement of the new arithmetic units over previous pertinent works. Consequently, the FFT and decimal co-processors designed in this thesis work with at least 10% higher speed than that of previous works. These architectures are meant to fulfill the demand for the high-speed co-processors required in various applications such as multimedia services and financial computations.

This thesis deals with the design of cost-effective large-scale RFID networks from both software and hardware aspects. To start with, different computer-aided tools were developed to maximize performance. The first set of algorithms focused on the elimination of redundant readers to minimize the cost and interference in large-scale RFID networks. For validation, uniform reader coverage was assumed, as widely used in most available publications. Then, both omni-directional and directional commercial reader antenna data were included for more reliability. Besides redundancy, an efficient physical placement of readers was also investigated by considering both uniform and random distribution over space. For this purpose, genetic-based algorithms have been proposed to increase reader coverage using commercial reader antenna beams. Energy consumption is also a critical design parameter for dense RFID networks. Therefore, a third set of algorithms was developed to efficiently minimize the energy consumption of large-scale RFID systems. Note that all above optimization techniques were achieved without compromising the whole RFID network performance. To further optimize cost and performance of large-scale RFID networks, a hardware approach through reader antenna design has been considered. In fact, since different RFID frequency bands have been assigned worldwide, large-scale RFID networks implemented in industrial parks, airports, or international trade zones, may deal with imported merchandise using tags operating at different frequencies. Therefore, in-house single and dual-band microstrip and CPW fed monopole antennas were successfully designed and tested to improve system adaptability to various RFID standards. These antennas were designed using both electromagnetic commercial simulators (HFSS) and in-house FDTD-based techniques. Finally, to further extend dense RFID network capabilities, one may implement a substantial number of readers and antennas with small reading ranges to cover a large monitoring area, or use high gain phased array antenna system for an extended reading range of an RFID reader for a smaller number of total reader deployments. Therefore, a phased antenna array system can be an efficient alternative for dense RFID networks. Thus, a switched beam network to control the phase of the radiating elements of the array has been successfully designed and tested.

Joining of uniformly-curved composite sandwich panel segments, typical in state of the art aerospace launch vehicles, should be mass-efficient. Adhesively bonded joints can provide increased mass-efficiency over mechanically-fastened joints. But, due to manufacturing sensitivities and certification requirements, conventional bonded joints can be improved upon by introducing structural redundancy. A longitudinal, durable redundant joint (DRJ) architecture featuring multiple adhesive load-paths, via a novel composite preform insert, was proposed to join composite sandwich panel segments of the interstage element for NASA's Ares V launch vehicle. A series of twenty-five static linear-elastic finite element models with plane strain solutions were developed to assess certain characteristics of a joint's structural response when subjected to a simplified circumferential hoop loading convention. Shear and normal stress distributions at the adherend-adhesive interface along the splice plate bondline of the DRJ are compared with those from a conventional splice joint (CSJ) configuration for a series of linearly increasing bondlines thicknesses and joint overlap lengths. The parameter studies indicate the DRJ configuration's adhesive peak stresses are independent of the joint overlap length at the joint edges. Also, simulated bonding defects, in the form of local adhesive gaps, due to manufacturing processes are investigated to determine the load path redistribution for the DRJ and CSJ configurations. Results for pristine versions of both configurations are included. The defective CSJ joint exhibits severe overloading of certain laminates, while the defective DRJ load redistributions are relatively mild. Between the two primary types of bondline gaps considered for the DRJ configuration, the gap corresponding to the splice plate, a more mature manufacturing operation and also a more easily inspected location than the insert-to-face sheet interface, is noted to be more severe. A direct joint-to-joint mass-comparison reveals a 164% increase in mass, per unit thickness, between the CSJ and DRJ. To put this in perspective, a second comparison is made using a four-segment sandwich panel barrel. A 3.51% increase in mass is observed between the CSJ and DRJ-based cylinders. Also, for a simplified sizing philosophy, based solely on the peak stresses in the adhesive domain, a CSJ may require a 1.5-inch longer joint overlap than a DRJ. The mass-estimate is recomputed, and the mass percent-increase of the segmented cylinder is reduced to 2.61% over a CSJ configuration. / Master of Science

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