The IEEE standard of decimal floating-point arithmetic was officially released in 2008. The new decimal floating-point (DFP) format and arithmetic can be applied to remedy the conversion error caused by representing decimal floating-point numbers in binary floating-point format and to improve the computing performance of the decimal processing in commercial and financial applications. Nowadays, many architectures and algorithms of individual arithmetic functions for decimal floating-point numbers are proposed and investigated (e.g., addition, multiplication, division, and square root). However, because of the less efficiency of representing decimal number in binary devices, the area consumption and performance of the DFP arithmetic units are not comparable with the binary counterparts. IBM proposed a binary fused multiply-add (FMA) function in the POWER series of processors in order to improve the performance of floating-point computations and to reduce the complexity of hardware design in reduced instruction set computing (RISC) systems. Such an instruction also has been approved to be suitable for efficiently implementing not only stand-alone addition and multiplication, but also division, square root, and other transcendental functions. Additionally, unconventional number systems including digit sets and encodings have displayed advantages on performance and area efficiency in many applications of computer arithmetic. In this research, by analyzing the typical binary floating-point FMA designs and the design strategy of unconventional number systems, ``a high performance decimal floating-point fused multiply-add (DFMA) with redundant internal encodings" was proposed. First, the fixed-point components inside the DFMA (i.e., addition and multiplication) were studied and investigated as the basis of the FMA architecture. The specific number systems were also applied to improve the basic decimal fixed-point arithmetic. The superiority of redundant number systems in stand-alone decimal fixed-point addition and multiplication has been proved by the synthesis results. Afterwards, a new DFMA architecture which exploits the specific redundant internal operands was proposed. Overall, the specific number system improved, not only the efficiency of the fixed-point addition and multiplication inside the FMA, but also the architecture and algorithms to build up the FMA itself. The functional division, square root, reciprocal, reciprocal square root, and many other functions, which exploit the Newton's or other similar methods, can benefit from the proposed DFMA architecture. With few necessary on-chip memory devices (e.g., Look-up tables) or even only software routines, these functions can be implemented on the basis of the hardwired FMA function. Therefore, the proposed DFMA can be implemented on chip solely as a key component to reduce the hardware cost. Additionally, our research on the decimal arithmetic with unconventional number systems expands the way of performing other high-performance decimal arithmetic (e.g., stand-alone division and square root) upon the basic binary devices (i.e., AND gate, OR gate, and binary full adder). The proposed techniques are also expected to be helpful to other non-binary based applications.

Every positive integer has a unique radix 2 representation which uses the digits {0,1}. However, if we allow digits other than 0 and 1, say {0,1,-1}, then a positive integer has many representations. Of these <i>redundant</i> representations, it is possible to choose one that has few nonzero digits. It is well known that using representations of integers with few nonzero digits allows certain algebraic operations to be done more quickly. This thesis is concerned with various representations of integers that are related to efficient implementations of algebraic operations in cryptographic algorithms. The topics covered here include: <ul> <li> <i>The width-w nonadjacent form (w-NAF)</i>. We prove that the <i>w</i>-NAF of an integer has a minimal number of nonzero digits; that is, no other representation of an integer, which uses the <i>w</i>-NAF digits, can have fewer nonzero digits than its <i>w</i>-NAF. </li> <li><i>A left-to-right analogue of the w-NAF</i>. We introduce a new family of radix 2 representations which use the same digits as the <i>w</i>-NAF, but have the property that they can be computed by sliding a window from left to right across the binary representation of an integer. We show these new representations have a minimal number of nonzero digits. </li> <li><i>Joint representations</i>. Solinas introduced a {0,1,-1}-radix 2 representation for pairs of integers called the joint sparse form. We consider generalizations of the joint sparse form which represent <i>r</i>&ge;2 integers and use digits other than {0,1,-1}. We show how to construct a {0,1,2,3}-joint representation that has a minimal number of nonzero columns. </li> <li><i>Nonadjacent digit sets</i>. It is well known that if <i>x</i> equals 3 or -1 then every nonnegative integer has a unique {0,1,<i>x</i>}-nonadjacent form; that is, a {0,1,<i>x</i>}-radix 2 representation with the property that, of any two consecutive digits, at most one is nonzero. We investigate what other values of <i>x</i> have this property. </li> </ul>

Evolution of Helicoverpa armigera resistance to Bacillus thuringiensis (Bt) cotton producing Cry1Ac is progressing in northern China, and replacement of Cry1Ac cotton by pyramided Bt cotton has been considered to counter such resistance. Here, we investigated four of the eight conditions underlying success of the refuge strategy for delaying resistance to Cry1Ac+Cry2Ab cotton, a pyramid that has been used extensively against H.armigera outside China. Laboratory bioassays of a Cry2Ab-selected strain (An2Ab) and a related unselected strain (An) reveal that resistance to Cry2Ab (130-fold) was nearly dominant, autosomally inherited, and controlled by more than one locus. Strong cross-resistance occurred between Cry2Ab and Cry2Aa (81-fold). Weaker cross-resistance (18- to 22-fold) between Cry2Ab and Cry1A toxins was also present and significantly increased survival of An2Ab relative to An on cotton cultivars producing the fusion protein Cry1Ac/Cry1Ab or Cry1Ac. Survival on Cry1Ac+Cry2Ab cotton was also significantly higher in An2Ab than in An, showing that redundant killing on this pyramid was incomplete. Survival on non-Bt cotton did not differ significantly between An2Ab and An, indicating an absence of fitness costs affecting this trait. These results indicate that a switch to three-toxin pyramided cotton could be valuable for increasing durability of Bt cotton in China.

Master of Science / Department of Electrical and Computer Engineering / Balasubramaniam Natarajan / Space-time coding (STC) schemes for Multiple Input Multiple Output (MIMO) systems have been an area of active research in the past decade. In this thesis, we propose a novel design of Space-Time Block Codes (STBCs) using Redundant Residue Number System (RRNS) codes, which are ideal for high data rate communication systems. Application of RRNS as a concatenated STC scheme to a MIMO wireless communication system is the main motivation for this work. We have optimized the link between residues and complex constellations by incorporating the “Direct Mapping” scheme, where residues are mapped directly to Gray coded constellations. Knowledge of apriori probabilities of residues is utilized to implement a probability based “Distance-Aware Direct Mapping” (DA) scheme, which uses a set-partitioning approach to map the most probable residues such that they are separated by the maximum possible distance. We have proposed an “Indirect Mapping” scheme, where we convert the residues back to bits before mapping them. We have also proposed an adaptive demapping scheme which utilizes the RRNS code structure to reduce the ML decoding complexity and improve the error performance. We quantify the upper bounds on codeword and bit error probabilities of both Systematic and Non-systematic RRNS-STBC and characterize the achievable coding and diversity gains assuming maximum likelihood decoding (MLD). Simulation results demonstrate that the DA Mapping scheme provides performance gain relative to a Gray coded direct mapping scheme. We show that Systematic RRNS-STBC codes provide superior performance compared to Nonsystematic RRNS-STBC, for the same code parameters, owing to more efficient binary to residue mapping. When compared to other concatenated STBC and Orthogonal STBC (OSTBC) schemes, the proposed system gives better performance at low SNRs.

The potential failure in through-silicon vias (TSVs) still poses a challenge in trying to extend the useful life of a 3D integrated circuit (IC). A model is proposed to mitigate the communication problem in 3D integrated circuits caused by the breaks at the TSVs. We provide the details of a low-complexity network that takes advantages of redundant TSVs to make it possible to re-route around breaks and maintain effective communication between layers. Different configurations for the micronetwork are analyzed and discussed. We also present an evaluation of the micronetwork's performance, which turns out to be quite promising, based on several Monte Carlo simulations. Finally, we provide some directions for future research on the subject.

No description available.

<p>This master thesis studies how much the cycle time, i.e. the time it takes for an industrial robot to perform a given task, can be reduced if an extra degree of freedom (DOF) is added to the robot system. The extra DOF consists of a linear track, which is supposed to be used in an optimal way. The problem has been studied using simulations in the robot simulation tool RobotStudio. </p><p>To be able to run an optimization in Matlab, with the RobotStudio simulation cycle time as the object function, communication between Matlab and RobotStudio has been set up with an interface written in Visual Basic. An algorithm has been developed to solve the problem. Two different optimization methods have been examined and compared. </p><p>The resulting algorithm has been applied to test cases. The results show that the cycle time in several cases can be reduced by 20-30 percent, if the movements along the track are optimized with the suggested method.</p>

Analog-to-digital converters are inevitable in the modern communication systems and there is always a need for the design of low-power converters. There are different A/D architectures to achieve medium resolution at medium speeds and among all those Cyclic/Algorithmic structure stands out due to its low hardware complexity and less die area costs. This thesis aims at discussing the ongoing trend in Cyclic/Algorithmic ADCs and their functionality. Some design techniques are studied on how to implement low power high resolution A/D converters. Also, non-ideal effects of SC implementation for Cyclic A/D converters are explored. Two kinds of Cyclic A/D architectures are compared. One is the conventional Cyclic ADC with RSD technique and the other is Cyclic ADC with Correlated Level Shift (CLS) technique. This ADC is a part of IMST Design + Systems International GmbH project work and was designed and simulated at IMST GmbH. This thesis presents the design of a 12-bit, 1 Msps, Cyclic/Algorithmic Analog-to-Digital Converter (ADC) using the “Redundant Signed Digit (RSD)” algorithm or 1.5-bit/stage architecture with switched-capacitor (SC) implementation. The design was carried out in 130nm CMOS process with a 1.5 V power supply. This ADC dissipates a power of 1.6  mW when run at full speed and works for full-scale input dynamic range. The op-amp used in the Cyclic ADC is a two-stage folded cascode structure with Class A output stage. This op-amp in typical corner dissipates 631 uW power at 1.5 V power supply and achieves a gain of 77 dB with a phase margin of 64° and a GBW of 54 MHz at 2 pF load.

This master thesis studies how much the cycle time, i.e. the time it takes for an industrial robot to perform a given task, can be reduced if an extra degree of freedom (DOF) is added to the robot system. The extra DOF consists of a linear track, which is supposed to be used in an optimal way. The problem has been studied using simulations in the robot simulation tool RobotStudio. To be able to run an optimization in Matlab, with the RobotStudio simulation cycle time as the object function, communication between Matlab and RobotStudio has been set up with an interface written in Visual Basic. An algorithm has been developed to solve the problem. Two different optimization methods have been examined and compared. The resulting algorithm has been applied to test cases. The results show that the cycle time in several cases can be reduced by 20-30 percent, if the movements along the track are optimized with the suggested method.

Every positive integer has a unique radix 2 representation which uses the digits {0,1}. However, if we allow digits other than 0 and 1, say {0,1,-1}, then a positive integer has many representations. Of these <i>redundant</i> representations, it is possible to choose one that has few nonzero digits. It is well known that using representations of integers with few nonzero digits allows certain algebraic operations to be done more quickly. This thesis is concerned with various representations of integers that are related to efficient implementations of algebraic operations in cryptographic algorithms. The topics covered here include: <ul> <li> <i>The width-w nonadjacent form (w-NAF)</i>. We prove that the <i>w</i>-NAF of an integer has a minimal number of nonzero digits; that is, no other representation of an integer, which uses the <i>w</i>-NAF digits, can have fewer nonzero digits than its <i>w</i>-NAF. </li> <li><i>A left-to-right analogue of the w-NAF</i>. We introduce a new family of radix 2 representations which use the same digits as the <i>w</i>-NAF, but have the property that they can be computed by sliding a window from left to right across the binary representation of an integer. We show these new representations have a minimal number of nonzero digits. </li> <li><i>Joint representations</i>. Solinas introduced a {0,1,-1}-radix 2 representation for pairs of integers called the joint sparse form. We consider generalizations of the joint sparse form which represent <i>r</i>&ge;2 integers and use digits other than {0,1,-1}. We show how to construct a {0,1,2,3}-joint representation that has a minimal number of nonzero columns. </li> <li><i>Nonadjacent digit sets</i>. It is well known that if <i>x</i> equals 3 or -1 then every nonnegative integer has a unique {0,1,<i>x</i>}-nonadjacent form; that is, a {0,1,<i>x</i>}-radix 2 representation with the property that, of any two consecutive digits, at most one is nonzero. We investigate what other values of <i>x</i> have this property. </li> </ul>