A recent trend in software industry is to provide enterprise applications in the cloud that are accessible everywhere and on any device. As the market is highly competitive, customer orientation plays an important role. Companies therefore start providing applications as a service, which are directly configurable by customers in an online self-service portal. However, customer configurations are usually deployed in separated application instances. Thus, each instance is provisioned manually and must be maintained separately. Due to the induced redundancy in software and hardware components, resources are not optimally utilized. A multi-tenant aware application architecture eliminates redundancy, as a single application instance serves multiple customers renting the application. The combination of a configuration self-service portal with a multi-tenant aware application architecture allows serving customers just-in-time by automating the deployment process. Furthermore, self-service portals improve application scalability in terms of functionality, as customers can adapt application configurations on themselves according to their changing demands. However, the configurability of current multi-tenant aware applications is rather limited. Solutions implementing variability are mainly developed for a single business case and cannot be directly transferred to other application scenarios. The goal of this thesis is to provide a generic framework for handling application variability, automating configuration and reconfiguration processes essential for self-service portals, while exploiting the advantages of multi-tenancy. A promising solution to achieve this goal is the application of software product line methods. In software product line research, feature models are in wide use to express variability of software intense systems on an abstract level, as features are a common notion in software engineering and prominent in matching customer requirements against product functionality. This thesis introduces a framework for feature-based configuration management of reconfigurable cloud applications. The contribution is three-fold. First, a development strategy for flexible multi-tenant aware applications is proposed, capable of integrating customer configurations at application runtime. Second, a generic method for defining concern-specific configuration perspectives is contributed. Perspectives can be tailored for certain application scopes and facilitate the handling of numerous configuration options. Third, a novel method is proposed to model and automate structured configuration processes that adapt to varying stakeholders and reduce configuration redundancies. Therefore, configuration processes are modeled as workflows and adapted by applying rewrite rules triggered by stakeholder events. The applicability of the proposed concepts is evaluated in different case studies in the industrial and academic context. Summarizing, the introduced framework for feature-based configuration management is a foundation for automating configuration and reconfiguration processes of multi-tenant aware cloud applications, while enabling application scalability in terms of functionality.

The downscaling of transistors is assumed to come to an end within the next years, and the semiconductor nonvolatile memories are facing the same physical downscaling challenge. Therefore, it is necessary to consider new computing paradigms and new memory concepts. Resistive switching devices (also referred to as memristive switches) are two-terminal passive device, which offer a nonvolatile switching behavior by applying short bias pulses. They have been considered as one of the most promising candidates for next generation memory and nonvolatile logic applications. They provide the possibility to carry out the information processing and storage simultaneously using the same resistive switching device. This dissertation focuses on the fabrication and characterization of BiFeO3 (BFO)-based metal-insulator-metal (MIM) devices in order to exploit the potential applications in nonvolatile memory and nonvolatile reconfigurable logics. Electroforming-free bipolar resistive switching was observed in MIM structures with BFO single layer thin film. The resistive switching mechanism is understood by a model of a tunable bottom Schottky barrier. The oxygen vacancies act as the mobile donors which can be redistributed under the writing bias to change the bottom Schottky barrier height and consequently change the resistance of the MIM structures. The Ti atoms diffusing from the bottom electrode act as the fixed donors which can effectively trap and release oxygen vacancies and consequently stabilize the resistive switching characteristics. The resistive switching behavior can be engineered by Ti implantation of the bottom electrodes. MIM structures with BiFeO3/Ti:BiFeO3 (BFO/BFTO) bilayer thin films show nonvolatile resistive switching behavior in both positive and negative bias range without electroforming process. The resistance state of BFO/BFTO bilayer structures depends not only on the writing bias, but also on the polarity of reading bias. For reconfigurable logic applications, the polarity of the reading bias can be used as an additional logic variable, which makes it feasible to program and store all 16 Boolean logic functions simultaneously into the same single cell of BFO/BFTO bilayer MIM structure in three logic cycles. / Die Herunterskalierung von Transistoren für die Informationsverarbeitung in der Halbleiterindustrie wird in den nächsten Jahren zu einem Ende kommen. Auch die Herunterskalierung von nichtflüchtigen Speichern für die Informationsspeicherung sieht ähnlichen Herausforderungen entgegen. Es ist daher notwendig, neue IT-Paradigmen und neue Speicherkonzepte zu entwickeln. Das Widerstandsschaltbauelement ist ein elektrisches passives Bauelement, in dem ein der Widerstand mittels elektrischer Spannungspulse geändert wird. Solche Widerstandsschaltbauelemente zählen zu den aussichtsreichsten Kandidaten für die nächste Generation von nichtflüchtigen Speichern sowie für eine rekonfigurierbare Logik. Sie bieten die Möglichkeit zur gleichzeitigen Informationsverarbeitung und -speicherung. Der Fokus der vorliegenden Arbeit liegt bei der Herstellung und der Charakterisierung von BiFeO 3 (BFO)-basierenden Metal-insulator-Metall (MIM) Strukturen, um zukünftig deren Anwendung in nichtflüchtigen Speichern und in rekonfigurierbaren Logikschaltungen zu ermöglichen. Das Widerstandsschalten wurde in MIM-Strukturen mit einer BFO-Einzelschicht untersucht. Ein besonderes Merkmal von BFO-basierten MIM-Strukturen ist es, dass keine elektrische Formierung notwendig ist. Der Widerstandsschaltmechnismus wird durch das Modell einer variierten Schottky-Barriere erklärt. Dabei dienen Sauerstoff-Vakanzen im BFO als beweglichen Donatoren, die unter der Wirkung eines elektrischen Schreibspannungspulses nichtflüchtig umverteilt werden und die Schottky-Barriere des Bottom-Metallkontaktes ändern. Dabei spielen die während der Herstellung von BFO substitutionell eingebaute Ti-Donatoren in der Nähe des Bottom-Metallkontaktes eine wesentliche Rolle. Die Ti-Donatoren fangen Sauerstoff-Vakanzen beim Anlegen eines positiven elektrischen Schreibspannungspulses ein oder lassen diese beim Anlegen eines negativen elektrischen Schreibspannungspules wieder frei. Es wurde gezeigt, dass die Ti-Donatoren auch durch Ti-Implantation der Bottom-Elektrode in das System eingebracht werden können. MIM-Strukturen mit BiFeO 3 /Ti:BiFeO 3 (BFO/BFTO) Zweischichten weisen substitutionell eingebaute Ti-Donatoren sowohl nahe der Bottom-Elektrode als auch nahe der Top-Elektrode auf. Sie zeigen nichtflüchtiges, komplementäres Widerstandsschalten mit einer komplementär variierbaren Schottky-Barriere an der Bottom-Elektrode und an der Top-Elektrode ohne elektrische Formierung. Der Widerstand der BFO/BFTO-MIM-Strukturen hängt nicht nur von der Schreibspannung, sondern auch von der Polarität der Lesespannung ab. Für die rekonfigurierbaren logischen Anwendungen kann die Polarität der Lesespannung als zusätzliche Logikvariable verwendet werden. Damit gelingt die Programmierung und Speicherung aller 16 Booleschen Logik-Funktionen mit drei logischen Zyklen in dieselbe BFTO/BFO MIM-Struktur.

Ausgehend von einer modularen Plattform zur Erfassung und Verarbeitung von Sensordaten bereichert die vorliegende Dissertationsschrift den Systementwurf eingebetteter Systeme um neue Facetten. Ihr besonderer Fokus liegt dabei auf rekonfigurierbaren Architekturen und Linux-basierten Systemen. Ein wesentlicher Beitrag ist die Darstellung und Diskussion von Konzepten und Architekturen vorgenannter Systeme durch ihre Betrachtung auf einer hohen Abstraktionsebene. Dazu schafft die Arbeit ein umfassendes Verständnis für Kommunikation und Konfiguration in heterogenen rekonfigurierbaren Systemen und überträgt die Erkenntnisse auf das Linux-Betriebssystem. Es erfolgt außerdem eine systematische Darstellung der etablierten Zusammenhänge und Abläufe beim Software-, Paket- und Versionsmanagement im Linux-Umfeld. Zur Verbesserung des Entwurfsflusses werden Konzepte und ein geeignetes Werkzeug zur High-Level Spezifikation von Linux-Systemen dargestellt. Die in der Arbeit gewonnenen wissenschaftlichen Erkenntnisse werden hinsichtlich praktischer Relevanz evaluiert und durch prototypische Implementierungen verifiziert. / Based on a modular platform for recording and processing of sensor data the present thesis enriches the field of system design of embedded systems with new facets. Its particular focus is on reconfigurable architectures and Linux-based systems. A major contribution is the presentation and discussion of concepts and architectures of aforementioned systems by investigating them on a high level of abstraction. To achieve this, the work creates a comprehensive understanding of communication and configuration in heterogeneous reconfigurable systems. This knowledge is transferred on the Linux operating system. In addition, a systematic presentation of the established relationships and processes in software, package and version management in the Linux environment takes place. To improve the design flow of Linux systems, the thesis presents appropriate concepts as well as a tool for high-level specification of embedded Linux systems. The gained scientific findings are evaluated in terms of practical relevance and verified by prototype implementations.

Tile-based many-core architectures are extensively used in modern system-on-chip designs to achieve scalable computing performance with adequate energy efficiency. Heterogeneity is the key element to boost computing performance and keep energy consumption under certain limits for several application domains. However, the steady increase of using many custom heterogeneous tiles leads to an expansion in design and integration cost with limited tiles re-usability. The recent widespread of open-source RISC-V ISA provides the potential to develop modular compute units that can be used for many application domains with high reduction in non-recurring engineering costs. The motivation of this work is to bring design modularity and adaptability features for heterogeneous tile-based many-core architectures by increasing their flexibility to realize different many-core configurations with less design time and costs. In this work, AGILER is proposed as an adaptive tile-base many-core architecture for heterogeneous RISC-V based processors. The proposed architecture consists of modular and adaptable heterogeneous multi-/single-core compute tiles that supports 32-/64-bit RISC-V ISAs with different memory hierarchies. Inter-tile communication is developed based on a scalable network-on-chip architecture to achieve a high degree of system scalability. AGILER supports run-time adaptation through a custom internal reconfiguration manager for dynamic and partial reconfiguration over Xilinx FPGAs. Evaluation results demonstrate that the proposed architecture features a scalable computing performance up to 685 MOPS for 8 x 32-bit tiles and 316 MOPS for 8 x 64-bit tiles with a scalable memory bandwidth up to 7.4 GB/s. AGILER is evaluated on Xilinx Virtex UltrascaleC FPGA with a maximum reconfiguration time of 38.1 ms for a single compute tile.