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Reliability Theoretic Measures of Importance of Components within Monotone SystemsDrigo, Gino 31 October 2006 (has links)
Student Number : 9804484F
MSc dissertation -
School of Statistics and Acturial Science -
Faculty of Science / This dissertation conducts a comprehensive and up to date review of measures of component and module importance within monotone systems, where it is assumed that components work independent of each other. The dissertation traces the development of these important measures from the initial definition of Birnbaum importance right through to the definition of Meng's criticality importance. Furthermore, the dissertation draws a distinction between time independent measures and time dependent measures (such as the Barlow-Proschan measures). The dissertation demonstrates how such measures may be implemented in analysing the importance of components within the monotone systems by evaluating these measures for a well known bridge structure example. This evaluation also reveals how each defined measure can be compared to each other. In conclusion, the dissertation describes how these measures can be extended to non-monotone systems or systems with dependent components.
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A Comparison of EDMOS and Cascode Structures for PA Design in 65 nm CMOS TechnologyAl-Taie, Mahir Jabbar Rashid January 2013 (has links)
This thesis addresses the potential of implementing watt-level class-AB Power Amplifier (PA) for WLAN in 65 nm CMOS technology, at 2.4 GHz frequency. In total, five PAs have been compared, where the examined parameters were output power (Pout), linearity, power added efficiency (PAE), and area consumption. Four PAs were implemented using conventional cascode topology with different combination of transistors sizes in 65nm CMOS, and one PA using a high-voltage Extended Drain MOS (EDMOS) device, implemented in the same 65 nm CMOS with no process or mask changes. All schematics were created using Cadence Virtuoso CAD tools. The test benches were created using the Agilent's Advance Design System ( ADS) and simulated with the ADS-Cadence dynamic link. The simulation results show that the EDMOS PA (L=350 nm) has the smallest area, but has harder to reach the required Pout. Cascode no. 3 (L= 500,260 nm) has the best Pout (29.1 dBm) and PAE (49.5 %). Cascode no. 2 (L= 500,350 nm) has the best linearity (low EVM). Cascode no. 1 (L=500,500 nm) has low Pout (27.7 dBm). Cascode no.4 (L=500,60 nm) has very bad linearity. The thesis also gives an overview for CMOS technology, discusses the most important aspects in RF PAs design, such as Pout, PAE, gain, and matching networks. Different PA classes are also discussed in this thesis.
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Informacinių įrenginių maitinimo projektavimo praktikos tyrimas / Research of designing practice for computer devices power supplyStalnionis, Laurynas 19 June 2006 (has links)
Informational equipment are difficult systems which performance reliability depends on a number of internal and external factors. One of the most important external factors is the quality of supplied electricity. Dependence of performance reliability of informational equipment upon the quality of supplied electricity, the impact of equipment themselves on the feeding system/net are discussed in this work. The standards of quality of electricity are overviewed, the deviations of voltage and their influence over informational equipment are evaluated. Means of increase of reliability, their structure and course of performance are described, their advantages and weaknesses are specified. Electrical ground system has major influence over reliable performance. In case of incorrect installation of the system it is possible to cause system foul-ups or even put a human life at risk. The influence of informational equipment over feeding net/system is evaluated in this work, the example of calculation of workload is presented.
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Design of a predriver for an EDMOS-based Class-D power amplifierMohsin, Taif January 2013 (has links)
This thesis addresses the potential of implementing a predriver for class-D power amplifier for WLAN in 65 nm CMOS technology. In total, eight different predrivers have been created using Cadence Virtuoso CAD tools. All designs have been tested using Agilent's Advance Design System (ADS) and simulated using the ADS-Cadence dynamic link. Furthermore, a comparison between the eight designs and the reference design has been done. The examined parameters were output power (Pout), efficiency, and effective area consumption. The simulation results show that most of the proposed designs obtain higher output power, higher efficiency, and lower effective area than the reference design. For the reference design, output power of 34.2 dBm, efficiency of 20.8 %, and effective area of 63952 um2 were obtained. For design No.1, the effective area was 31511um2, which was almost half of the area occupied by the reference design. For design No.3, the efficiency was 71.2 %, which was almost 3 and half times higher than the efficiency of the reference design. Furthermore, all designs, except design NO.7, gave more or less the same output power (around 34.4 dBm).
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