With the advancement of semiconductor technology, the System on Chip (SoC) is becoming more and more complex, so the on-chip communication has become a bottleneck of SoC Design. Since the traditional bus system is inefficient and not scalable, the Network-On-Chip (NoC) has emerged as the promising communication mechanism for complex SoCs. As some systems have specific performance requirements, such as a minimum throughput (for real-time streaming data) or bounded latency (for interrupts, process synchronization, etc), communication with Guaranteed Service (GS) support becomes crucial for predictable SoC architectures. Circuit Switching (CS) is a popular approach to support GS, which firstly has to allocate an exclusively connection (circuit) between the source and destination nodes, and then the data packets are delivered over this connection. However, it is inefficient and inflexible because the resource is occupied by single connection during its whole lifetime, which can block other communications. Hence, two extensions of CS have been proposed to share resources: i) Time-Division Multiplexing (TDM), in which the available link capacity is split into multiple time slots to be shared by different flows in TDM scheme; and ii) Space-Division-Multiplexing (SDM), in which only a subset (sub-channel) of the link wires is exclusively allocated to a specific connection, while the remaining wires of the link can be used by other flows. The connection allocation is critical for CS, since the data delivery can start only after the associated connection is allocated. In this thesis, we propose a dedicated hardware connection allocator to solve the dynamic connection allocation problem for CS NoCs, which has to i) allocate a contention-free path between source-destination pairs and ii) allocate appropriate portions of link bandwidth (appropriate number of time slots and subsets) along the path. The dedicated connection allocator, called NoCManager, solves the connection allocation problem by employing a trellis-search based shortest path algorithm. The trellis search can explore all possible paths between source node and destination. Moreover, it shall find the requested path in a fixed low latency and can guarantee the path optimality in terms of path length if the path is available. In this thesis, two different trellis graphs, Forward-Backtrack trellis and Register-Exchange trellis are proposed. The Forward-Backtrack trellis completes the path search in two steps: forward search and backtracking. Firstly, the forward search begins at source node that traverses the network to find the free path. When destination node is reached, the backtrack starts from destination to select the survivor path and collect the associated path parameters. However, Register-Exchange trellis saves the entire survivor path sequences during forward search. Consequently, the backtracking step can be omitted, and thus the allocation time is halved compared to forward-backtrack approaches. Moreover, each trellis graph consists of three categories, unfolded structure, folded structure and bidirectional structure. The unfolded structure can provide high allocation speed while folded structure is more efficient from a hardware point of view. The bidirectional structure starts the search at two sides, source node and destination node simultaneously, so the allocation speed is 2 times faster than previous unidirectional search. Furthermore, in order to address the scalability issue of previous centralized systems, the partitioned architecture (i.e. spatial partitioning technique) is proposed to divide the large system into multiple smaller differentiated logical partitions served by local NoCManagers. This partitioning technique keeps the request load of the manager and manager-node communication overhead moderate. Inside each partition, the path search problem is solved by a local manager with trellis-search algorithm. To establish a path that crosses partitions, the managers communicate with each other in distributed manner to converge the global path. In order to further enhance the path diversity and resource utilization, we adopt the combined TDM and SDM technique. In combined TDM-SDM approach, each SDM sub-channel is split into multiple time slots so that can be shared by multiple flows. Hence, the number of sub-channels can be kept moderate to reduce router complexity, while still providing higher path diversity than TDM scheme. In order to investigate and optimize TDM-SDM partitioning strategy, we studied the influence of different TDM-SDM link partitioning strategies on success rate and path length that allowed us to find the optimal solution. The dedicated connection allocator using the trellis-search algorithm is employed for TDM, SDM and TDM-SDM CS. In the end, we present the router architecture that combines the circuit-switching network (for GS communication) and packet-switching network (for best-effort communication).

Scaling of electronic circuits from micro- to nanometer size determined the incredible development in computer technology in the last decades. In charge storage capacitors that are the largest components in dynamic random access memories (DRAM), dielectrics with higher permittivity (high-k) were needed to replace SiO2. Therefore ZrO2 has been introduced in the capacitor stack to allow sufficient capacitance in decreasing structure sizes. To improve the capacitance density per cell area, approaches with three dimensional structures were developed in device fabrication. To further enable scaling for future generations, significant efforts to replace ZrO2 as high-k dielectric have been undertaken since the 1990s. In calculations, CaTiO3 has been identified as a potential replacement to allow a significant capacitance improvement. This material exhibits a significantly higher permittivity and a sufficient band gap. The scope of this thesis is therefore the preparation and detailed physical and electrical characterization of ultrathin CaTiO3 layers. The complete capacitor stacks including CaTiO3 have been prepared under ultrahigh vacuum to minimize the influence of adsorbents or contaminants at the interfaces. Various electrodes are evaluated regarding temperature stability and chemical reactance to achieve crystalline CaTiO3. An optimal electrode was found to be a stack consisting of Pt on TiN. Physical experiments confirm the excellent band gap of 4.0-4.2 eV for ultrathin CaTiO3 layers. Growth studies to achieve crystalline CaTiO3 indicate a reduction of crystallization temperature from 640°C on SiO2 to 550°C on Pt. This reduction has been investigated in detail in transmission electron microscopy measurements, revealing a local and partial epitaxial growth of (111) CaTiO3 on top of (111) Pt surfaces. This preferential growth is beneficial to the electrical performance with an increased relative permittivity of 55 with the advantage of a low leakage current comparable to that in amorphous CaTiO3 layers. A detailed electrical analysis of capacitors with amorphous and crystalline CaTiO3 reveals a relative permittivity of 30 for amorphous and an excellent value of 105 for fully crystalline CaTiO3. The permittivity exhibits a quadratic dependence with applied electric field. Crystalline CaTiO3 shows a 1-3% drop in capacitance density and permittivity at a bias voltage of 1V, which is significantly lower compared to all results for SrTiO3 capacitors measured elsewhere. A capacitance equivalent thickness (CET) below 1.0 nm with current densities 1×10−8 A/cm2 have been achieved on carbon electrodes. Finally, CETs of about 0.5 nm with leakage currents of 1 × 10−7 A/cm2 on top of Pt/TiN fulfill the 2016 DRAM requirements following the ITRS road map of 2012. / Die Verkleinerung von elektronischen Bauelementen hin zu nanometerkleinen Strukturen beschreibt die unglaubliche Entwicklung der Computertechnologie in den letzten Jahrzehnten. In Ladungsspeicherkondensatoren, den größten Komponenten in Arbeitsspeichern, wurden dafür Dielektrika benötigt, die eine deutlich höhere Permittivität als SiO2 besitzen. ZrO2 wurde als geeignetes Dielektrikum eingeführt, um eine ausreichende Kapazität bei kleiner werdenen Strukturen sicherzustellen. Zur weiteren Verbesserung der Kapazitätsdichte pro Zellfläche konnten 3D Strukturen in die Chipherstellung integriert werden. Seit den 1990ern wurden parallel bedeutende Anstrengungen unternommen, um ZrO2 als Dielektrikum durch Materialien mit noch höherer Permittivität zu ersetzen. Nach Berechnungen stellt nun CaTiO3 eine mögliche Alternative dar, die eine weitere Verbesserung der Kapazität ermöglicht. Das Material besitzt eine deutlich höhere Permittivität und eine ausreichend große Bandlücke. Diese Arbeit beschäftigt sich deshalb mit Herstellung und detaillierter physikalischer und elektrischer Charakterisierung von extrem dünnen CaTiO3 Schichten. Zusätzlich wurden diverse Elektroden bezüglich ihrer Temperaturstabilität und der chemischen Stabilität untersucht, um kristallines CaTiO3 zu herhalten. Als eine optimale Elektrode stellte sich Pt auf TiN heraus. Physikalische Experimente an extrem dünnen CaTiO3 Schichten bestätigen die Bandlücke von 4,0-4,2 eV. Wachstumsuntersuchungen an kristallinem CaTiO3 zeigen eine Reduktion der Kristallisationstemperatur von 640°C auf SiO2 zu 550°C auf Pt. Diese Reduktion wurde detailliert mittels Transmissionselektronenmikroskopie untersucht. Es konnte für einige Schichten ein partielles lokales epitaktischesWachstum von (111) CaTiO3 auf (111) Pt gemessen werden. Dieses Vorzugswachstum ist vorteilhaft für die elektrischen Eigenschaften durch eine gesteigerte Permittivität von 55 bei gleichzeitig geringem Leckstrom vergleichbar zu amorphen Schichten. Eine genaue elektrische Analyse von Kondensatoren mit amorphen und kristallinem CaTiO3 ergibt eine Permittivität von 30 für amorphe und bis zu 105 für kristalline CaTiO3 Schichten. Die Permittivität zeigt eine quadratische Abhängigheit von der angelegten Spannung. Kristallines CaTiO3 zeigt einen 1-3% Abfall der Permittivität bei 1V, der wesentlich geringer ausfällt als vergleichbare Werte für SrTiO3. Eine zu SiO2 vergleichbare Schichtdicke (CET) von unter 1,0 nm mit Stromdichten von 1×10−8 A/cm2 wurde auf Kohlenstoffsubstraten erreicht. Mit Werten von 0,5 nm bei Leckstromdichten von 1×10−7 A/cm2 auf Pt/TiN Elektroden erfüllen die CaTiO3 Kondensatoren die Anforderungen der ITRS Strategiepläne für Arbeitsspeicher ab 2016.