Metallized polypropylene film capacitors are prone to failure under high pulsed voltage and current waveforms. A set of specifications are given by the International Electrotechnical Commission (IEC) that defines the required performance characteristics of these capacitors. The proposed test setup is very involved and requires a skilled operator who is responsible for ensuring that the prescribed test conditions are accurately applied to the capacitor. Automated test and measurement equipment was developed to conduct these tests according to the IEC specifications. The test equipment generates large crest factor current discharge waveforms in the capacitor with peaks reaching 1000 A. A new method was also developed for measuring the rms value of these current waveforms using a low-end microcontroller, together with an inexpensive current transformer. The recommended IEC discharge circuit is powered by a switching power supply, utilizing feedback control, which also enables the rms current through the capacitor to be regulated. By automating the system, important responsibilities are isolated from the operator, allowing a less skilled person to effectively conduct the capacitor tests. / Prof. W.A. Cronje Prof. I.W. Hofsajer

The passive devices (such as resistor, capacitor, and inductor) in recent wireless communication system tend to occupy large area due to their inability to be integrated with IC in one chip. This paper presents an IC compatible tunable capacitor by using MEMS technology. This tunable capacitor is consist of one suspended top plate and two fixed bottom plates (signal electrode and bias electrode). By driving electrostatic force, the gap between top and bottom electrodes will be changed and result in capacitance variation. To increase the tuning range, the tunable capacitor with two different gap space will be involved in our design. Based on theory, 200% tuning range will be achieved. One the other hand, this paper present the processing of three different sacrificial layers : (1) photoresists (2) photoresist and metal (3) metals sacrificial layers.

Thesis (M. Phil.)--University of Hong Kong, 1988.

The motivation of this study is based on integrated passive filter dielectric thin films with thin layers. Reducing the area of integrated passive filter in a circuit by enhancing dielectric constant with same capacitance and thickness is the purpose which has been expected. To fabricate the thin film MIM structure capacitors, RF magnetron sputtering method was selected and BaNd2Ti5O14 composed materials treated as the target to grow the thin film dielectric layer in MIM structure capacitors. In this study the MIM structure capacitors were deposited on alumina substrates with Pt electrodes. In the thin film experiments, various operation parameters of sputtering deposition and post thermal process at different temperature were used to perform the desired thin film dielectric layers. In order to obtain the optimal performance of the dielectric thin films, ¡§Taguchi Method¡¨ was used as a experimental tool. The primary investigation focused on the electric characteristics of the thin film capacitors in this article. In the arranged ranges of the parameters, the optimal dielectric thin films were deposited under RF power 100W with deposition temperatures at 400¢J, chamber pressure is 10mtorr. The dielectric constant of deposited thin films is 39.2 at 1MHz, the dissipation factor is 1.38¢H at 10kHz, leakage current is 2.61X10-7A/cm2 at 5V operating voltage and breakdown electric field of 0.29MV/cm is observed. The crystalline structures of deposited thin films were characterized by XRD and found amorphous structure. Film roughness was measured by Atomic Force Microscope (AFM) with 0.263 nm.

No description available.

In this work a new voltage buffer, the drain-follower, achieves 300MHz band-width with 2pF load, a dc gain of 0.993V/V, 1mV offset voltage, -60 dB total harmonic distortion at 1.4Vpp output voltage and 6.5mW power dissipation from 5V supply. A unity-gain buffer switched-capacitor biquad filter has been implemented in 0.5��m CMOS technology. The circuit has been sent for fabrication. Simulation results of the biquad filter indicate operation at 100MHz with 20mW power consumption from a 5V supply can be achieved. / Graduation date: 2002

This thesis describes design techniques for high-performance switched-capacitor (SC) circuits, primarily for high-linearity low-noise SC circuits in the presence of component imperfections, such as nonlinear op-amp voltage transfer characteristics, capacitor nonlinearities as well as the finite op-amp dc gain and op-amp offset and noise. Various correlated-double-sampling (CDS) schemes are discussed, and some novel predictive CDS schemes are proposed. Analysis, simulation and experimental results show that these schemes are very effective for reducing the effects of op-amp imperfections, resulting in lower signal distortion and reduced low-frequency noise and dc offset. The effect of capacitor nonlinearity in an SC circuits is analyzed in detail, and techniques for linearization are discussed. Applying these techniques, MOSFET capacitors can be used in high-performance digital-process-compatible SC circuit designs. To verify the effectiveness of the proposed techniques, three prototype chips containing a 3-V all-MOSFET delta-sigma modulator, predictive gain- and offset-compensated track-and-hold stages, and SC amplifiers with various CDS techniques, were designed and fabricated in 1.2 ��m CMOS technology. The measured results show that these circuit techniques are highly effective in high-performance SC circuit designs. / Graduation date: 1997

As deregulation of the electric power system in the United States unfolds, many customers are experiencing changes in their billing rate structure. Some face the addition of power factor penalty tariffs, and seek ways to minimize the added burden. The installation of entrance capacitor banks is the common response, but fails to take complete advantage of capacitor abilities. Other project designs exist that can harness these advantages to the full benefit of the customer. This work will show that distributing shunt capacitors in parallel with induction motors will elevate power factor and voltage, and also decrease ohmic losses in the wiring and protection devices that supply the motor. This reduction often produces a better overall economic solution due to energy savings. The distribution of capacitors at induction motors reduces the reactive current in the branch of the distribution system that supplies them. A reduction in the total current flowing to the motor along the distribution system results in smaller losses throughout the system. As losses diminish, the total real power drawn through the distribution system is lessened, and electric bills are reduced. This alternative to entrance capacitor banks is not as commonly implemented. A misconception that the resistance in facility distribution systems is relatively low has discouraged distributed motor capacitor installation for overall facility power factor correction, in favor of entrance capacitor banks. We will show that the resistance in the distribution system is higher than typically thought, that motor capacitors can exploit this fact, and can often economically outperform entrance capacitor banks which are terminated at the point of incoming utility power. Motor capacitors are not a new technology. They are commercially available off the shelf technology, suitable for power factor correction for induction motors. Distributed capacitors can be utilized for all significantly sized induction motors in a facility. The elevation in power factor and voltage, reduction in reactive current and real power are calculated, and trends are observed. The matter is considered from both the standpoint of engineering and economics to provide an integrated study.

published_or_final_version / Electrical Engineering / Master / Master of Philosophy

No description available.