The passive devices (such as resistor, capacitor, and inductor) in recent wireless communication system tend to occupy large area due to their inability to be integrated with IC in one chip. This paper presents an IC compatible tunable capacitor by using MEMS technology. This tunable capacitor is consist of one suspended top plate and two fixed bottom plates (signal electrode and bias electrode). By driving electrostatic force, the gap between top and bottom electrodes will be changed and result in capacitance variation. To increase the tuning range, the tunable capacitor with two different gap space will be involved in our design. Based on theory, 200% tuning range will be achieved. One the other hand, this paper present the processing of three different sacrificial layers : (1) photoresists (2) photoresist and metal (3) metals sacrificial layers.

This paper aims to design and simulate the surface-micromachining micro tunable capacitor for parameters optimization. This work also creates an equivalent circuit model of micro tunable capacitor and proceeds relative electromechanical analysis, including the distribution of field and charge, resonant frequency and pull-in voltage analysis. This micro tunable capacitor is constructed by one suspended top metal plate and two stationary bottom metal plates (one is signal electrode and the other one is bias electrode). By driving electrostatic force, the gap between top and bottom electrodes will be changed and results in a variation of capacitance. To increase the tuning range, the micro tunable capacitor with two different gap space will be presented in this research. High frequency analysis, equivalent circuit analysis and electromechanical dynamic analysis are using Ansoft HFSS, Agilent ADS and the IntelliSuite software respectively. Through these simulation and analysis, it is possible to obtain the optimized specification of micro tunable capacitor. The quality factor (Q) and the pull-in voltage extracted by simulation software well match to the measured results; thus, the function of the analysis method and equivalent model adopted in this thesis can be demonstrated.

The passive devices used in the wireless communication system ¡]including resistor, capacitor and inductor¡^usually need high quality factor and low power dissipation characteristics. This thesis aims to develop a micro tunable capacitor with high-quality-factor and wide-tuning-range using surface micromachining. In contrast with conventional low-tuning-rate parallel-plate tunable capacitors, this research presents a concave structure and eight-suspending-beams layout design of the top electrode to enhance the elastic rigidity and tuning rate. In addition, this study appropriately decreases the thickness of top electrode, the tuning rate of such device can be improved to 65~2100%. On the other hand, in order to substantially increase quality factor, this thesis adopted the glass substrate ¡]Corning 7740¡^to reduce the power dissipation of high frequency operating signal. The optimized quality factor of this work is approximately equal to 41 under 2.4 GHz operation frequency. The material of sacrificial layer and top electrode adopted in this dissertation is aluminum and gold respectively. To avoid any breakage of the vertical supporting beams during releasing process, this research appropriately increases the width of vertical supporting beams, however, keep the thickness of the suspending part of top electrode for the maintenance of high quality factor and low driving voltage.

L’évolution des différentes générations de systèmes de télécommunications cellulaires a entraîné une complexité du frontal des terminaux mobiles caractérisés notamment par la multiplication des chaînes RF qui le constituent. Chaque chaîne est dédiée à un standard, ce qui n’est pas optimale ni du point de vue du coût, ni de l’encombrement. Afin d’optimiser les performances et la consommation du transmetteur radiofréquence, l’approche retenue dans cette thèse consiste à concevoir de façon globale différents blocs afin de partager les contraintes. Dans cette thèse, l’approche globale de la co-conception est organisée en deux sous études. Celles-ci sont destinées à terme à être intégrées dans un même frontal RF entièrement configurable.La première étude aborde la problématique de la conception conjointe entre une antenne et un amplificateur de puissance (PA) qui sont traditionnellement conçus séparément. Nous avons tout d’abord déterminé les spécifications de l’antenne permettant de maximiser le transfert d’énergie entre ces deux blocs. Ensuite, nous avons conçu l’antenne en partageant les contraintes d’impédance à la fois dans la bande utile et aux harmoniques entre cette dernière et le PA afin de relâcher les spécifications sur le réseau d’adaptation d’impédance. Cette approche permet de maintenir la linéarité du PA à des niveaux de puissances supérieures par rapport au cas où l’antenne est adaptée sur 50 Ω.La seconde étude s’intéresse à la conception conjointe d’antennes et de composants agiles. Nous avons réparti l’effort de miniaturisation et les pertes ohmiques associées entre la structure d’antenne et le composant agile (capacité commutable numériquement). Les développements présentés se sont appuyés sur des simulations électromagnétiques, des modélisations, des caractérisations système (linéarité et temps de commutation) et des mesures en rayonnement (efficacité) de prototypes d’antennes miniatures dans les bandes basses 4G. Nos études ont abouti à la conception d’une antenne fente reconfigurable fonctionnant sur la bande instantanée maximale autorisée par la 4G. Pour une intégration sur smartphone, l’élément rayonnant n’occupe que 18 x 3 mm2 de surface soit λ_0/30×λ_0/180 à 560 MHz. La fréquence de résonance de l’antenne varie entre 560 MHz et 1.03 GHz et l’efficacité totale varie entre 50% et 4%. Un banc de mesure de la linéarité a été implémenté afin d’évaluer la linéarité des antennes agiles. La spécification de linéarité exigée par le standard est maintenu jusqu’à une puissance de 22 dBm. / The recent development of cellular communication standards has led to an increasing RF front-end complexity due to the ever increasing number of RF needed paths. Each RF path is dedicated to a frequency bands group which might not be optimal for cost and occupied space area. Consequently, in order to optimize the RF performances and energy consumption, the approach used in this thesis is to share the constraints between the PA and the antenna of the front-end: this is called co-design. In this thesis, the considered co-design approach is twofold and in near future both results should be simultaneously considered and integrated into one fully reconfigurable RF front-end design.The first study addresses the co-design of an antenna and its associated power amplifier (PA), which are traditionally designed separately. We first determine the antenna impedance specifications to maximize the tradeoff between the energy transfer and PA linearity. Then, we propose to remove the impedance matching network between antenna and PA, while demonstrating that a low impedance antenna can maintain the RF performances. Contrarily to the classical approach where the antenna is matched to 50 Ω, the proposed co-design shows the possibility to keep the linearity of the PA even for high power levels (> 20 dBm).The second study focuses on the co-design of an antenna and tunable components. We are sharing the miniaturization effort and the resistive losses between the antenna structure and the tunable capacitor (DTC). The achieved developments are based on electromagnetic simulations, modeling, system characterization (linearity and switching time) and radiation measurements (efficiency) of miniature reconfigurable antenna prototypes in the 4G low bands. The considered studies have led to the design of a frequency reconfigurable antenna addressing the maximum instantaneous available bandwidth authorized by 4G. The radiator occupies only 18 x 3 mm2 (λ0/30 x λ0/180 at 560 MHz), and thus it is extremely suitable for a possible integration onto smartphones. The antenna resonance frequency is tuned between 560 MHz and 1030 MHz and the total efficiency varies between 50% and 4%. For the first time, the impact of SOI DTC implemented on the antenna radiating structure on linearity is measured with a dedicated test bench. The linearity specified by 4G is maintained up to 22 dBm of transmitted power.

Dans le contexte des applications mobiles, les contraintes de conception des chaînes d'émission toujours plus performantes et de taille réduite demandent de compenser la forte sensibilité des caractéristiques des antennes à leur environnement. En particulier, il est nécessaire de maîtriser l'impédance de l'antenne pour optimiser l'efficacité énergétique de la chaîne de transmission. Or, les solutions actuelles se montrent encombrantes. Dans cette thèse, plusieurs pistes basées sur l'implémentation de condensateurs variables ont été étudiées et ont conduit à la réalisation et la caractérisation de nouveaux dispositifs RF intégrés à même de participer à cet effort. Après une présentation du contexte et de l'état de l'art, nous proposons une étude de condensateurs variables basés sur la technique des capacités commutées. L'étude a permis la réalisation de deux condensateurs variables en technologie CMOS SOI 130 nm pour des applications d'adaptation d'impédance et d'antenne agile en fréquence. Un premier démonstrateur d'antenne fente agile en fréquence visant les bandes LTE situées entre 500 MHz et 1 GHz et utilisant ce type de condensateur a ensuite été réalisé puis validé. Un système d'accord permettant de corriger les désadaptations d'antenne a ensuite été étudié et a donné lieu à la réalisation de deux circuits intégrés en technologie CMOS SOI 130 nm. Le premier circuit est un détecteur d'impédance capable de fonctionner sur une gamme de puissance étendue de 0-40 dBm pour une plage de fréquences de 600 MHz-2,4 GHz. Le deuxième circuit intègre une version améliorée du détecteur avec un circuit d'adaptation variable autorisant la réalisation d'un système d'accord d'antenne autonome et compact représentant une avancée importante par rapport à l'état de l'art. / In the context of mobile applications, design constraints on always more performant and size-constrained emitting front-ends ask to compensate for strong sensitiveness of antennas characteristics to their environment. In particular, it is necessary to control the antenna impedance in order to optimize the energy efficiency of the transmitting front-end. Yet, current solutions are bulky. I this thesis, several ways based on the implementation of variable capacitors have been studied and have led to the design and characterization of new integrated RF devices that can participate to this effort. After a presentation of the context and the state-of-the-art, we propose a study of switched-capacitor-based variable capacitors. This study allowed the design of two variable capacitors in 130 nm CMOS SOI technology for impedance matching and frequency-agile antenna applications. Then, a first demonstrator module of a frequency-agile antenna aiming for 500 MHz-1 GHz LTE bands and using this type of capacitor has been designed and validated. A tunable system allowing the correction of antenna mismatch has then been studied and has led to the design of two 130 nm CMOS SOI integrated circuits. The first circuit is an impedance detector that is able to work on a 0-40 dBm power range and a 600 MHz-2.5 GHz frequency range. The second integrated circuit includes an improved version of the detector with a tunable matching network which both allow the fabrication of an autonomous, compact antenna tunable system showing significant progress relative to the state-of-the-art.

Contactless automatic identification procedures which are called RFID systems (Radio-frequency Identification) have become very popular in recent years for transferring power and data. With the development of RFID technology, the demand of easy transmitting of short data packages has made NFC (Near-field Communication) technology wildly used especially in mobile applications. The communication between a mobile and a tag is achieved through a magnetic field generated by the mobile’s NFC interface. In order to get a maximal power transmission, the tag circuit is designed to operate at the resonance frequency of 13.56 MHz, which is equal to the operation frequency of the mobile’s NFC interface. As mutual inductances provided by different kinds of mobiles exist divergence, optimal power transfer cannot be reached every time. This thesis focuses on the optimization of power transfer during the communications between tags and mobiles with uncertain NFC coils. By incorporating a self-tuning parallel variable capacitance compensation circuitry the resonance frequency of an NFC tag circuit can be self-tuned to 13.56 MHz to ensure an optimal power transmission. This thesis presents both theoretical and experimental analysis of this improved self-tuning NFC circuitry in detail and demonstrates that by digitally tuning a parallel capacitor circuit, the energy transferred to an NFC tag can be optimized when facing different kinds of NFC-enabled mobile phones.

The advances in modern communication systems have brought about devices with more functionality, better performance, smaller size, lighter weight and lower cost. Meanwhile, the requirement for newer devices has become more demanding than ever. Tunability and flexibility are both long-desired features. Tunable devices are ‘smart’ in the sense that they can adapt to the dynamic environment or varying user demand as well as correct the minor deviations due to manufacturing fluctuations, therefore making it possible to reduce system complexity and overall cost. It is also desired that electronics be flexible to provide conformability and portability. Previously, tunable devices on flexible substrates have been realized mainly by dicing and assembling. This approach is straightforward and easy to carry out. However, it will become a “mission impossible” when it comes to assembling a large amount of rigid devices on a flexible substrate. Moreover, the operating frequency is often limited by the parasitic effect of the interconnection between the diced device and the rest of the circuit on the flexible substrate. A recent effort utilized a strain-sharing Si/SiGe/Si nanomembrane to transfer a device onto a flexible substrate. This approach works very well for silicon based devices with small dimensions, such as transistors and varactor diodes. Large-scale fabrication capability is still under investigation. A new transfer technique is proposed and studied in this research. Tunable BST (Barium Strontium Titanate) IDCs (inter-digital capacitors) are first fabricated on a silicon substrate. The devices are then transferred onto a flexible LCP (liquid crystalline polymer) substrate using iv wafer bonding of the silicon substrate to the LCP substrate, followed by silicon etching. This approach allows for monolithic fabrication so that the transferred devices can operate in millimeter wave frequency. The tunability, capacitance, Q factor and equivalent circuit are studied. The simulated and measured performances are compared. BST capacitors on LCP substrates are also compared with those on sapphire substrates to prove that this transfer process does not impair the performance. A primary study of a reflectarray antenna unit cell is also conducted for loss and phase swing performance. The BST thin film layout and bias line positions are studied in order to reduce the total loss. Transferring a full-size BST-based reflectarray antenna onto an LCP substrate is the ultimate goal, and this work is ongoing at the University of Central Florida (UCF). HFSS is used to simulate the devices and to prove the concept. All of the devices are fabricated in the clean room at UCF. Probe station measurements and waveguide measurements are performed on the capacitors and reflectarray antenna unit cells respectively. This work is the first comprehensive demonstration of this novel transfer technique.

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The present work is dedicated to the development of high performance integrated circuits for wireless communications, by acting of three different levels: technologies, devices, and circuits. Silicon-on-Insulator (SOI) CMOS technology is used in the frame of this work. Micromachining technologies are also investigated for the fabrication of three-dimensional tunable capacitors. The reliability of micromachined thin-film devices is improved by the coating of silanes in both liquid- and vapor-phases. Since in telecommunication applications, distortion is responsible for the generation of spurious frequency bands, the linearity behavior of different SOI transistors is analyzed. The validity range of the existing low-frequency nonlinear characterization methods is discussed. New simple techniques valid at both low- and high-frequencies, are provided, based on the integral function method and on the Volterra series. Finally, the design of a crucial nonlinear circuit, the voltage-controlled oscillator, is introduced. The describing function formalism is used to evaluate the oscillation amplitude and is embedded in a design methodology. The frequency tuning by SOI varactors is analyzed in both small- and large-signal regimes.