As deregulation of the electric power system in the United States unfolds, many customers are experiencing changes in their billing rate structure. Some face the addition of power factor penalty tariffs, and seek ways to minimize the added burden. The installation of entrance capacitor banks is the common response, but fails to take complete advantage of capacitor abilities. Other project designs exist that can harness these advantages to the full benefit of the customer. This work will show that distributing shunt capacitors in parallel with induction motors will elevate power factor and voltage, and also decrease ohmic losses in the wiring and protection devices that supply the motor. This reduction often produces a better overall economic solution due to energy savings. The distribution of capacitors at induction motors reduces the reactive current in the branch of the distribution system that supplies them. A reduction in the total current flowing to the motor along the distribution system results in smaller losses throughout the system. As losses diminish, the total real power drawn through the distribution system is lessened, and electric bills are reduced. This alternative to entrance capacitor banks is not as commonly implemented. A misconception that the resistance in facility distribution systems is relatively low has discouraged distributed motor capacitor installation for overall facility power factor correction, in favor of entrance capacitor banks. We will show that the resistance in the distribution system is higher than typically thought, that motor capacitors can exploit this fact, and can often economically outperform entrance capacitor banks which are terminated at the point of incoming utility power. Motor capacitors are not a new technology. They are commercially available off the shelf technology, suitable for power factor correction for induction motors. Distributed capacitors can be utilized for all significantly sized induction motors in a facility. The elevation in power factor and voltage, reduction in reactive current and real power are calculated, and trends are observed. The matter is considered from both the standpoint of engineering and economics to provide an integrated study.

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This thesis mainly studies the active power factor correction circuit using a new AC/DC Single Ended Primary Inductance Converter (SEPIC). For power factor correction, inductor current is operated in the continuous conduction mode. First of all, the converter is analyzed by state space averaging method. Furthermore, the operational principle of PFC circuit with PI control law is analyzed. A good power factor system is then developed by time-domain and frequency-domain analysis. A classical PFC circuit with PI control law has low power factor when light load. In order to overcome problem, the thesis proposes a SEPIC circuit with robust performance. Compared with circuits using classical PI controller and PFC IC, the proposed system obtains higher power factor under the condition of the same light load.

Recent technological advances have allowed silicon (Si) semiconductor technology to approach the theoretical limits of the Si material; however, power device requirements for many applications are at a stage that the present Si-based power devices cannot handle. The requirements include higher blocking voltages, switching frequencies, efficiency, and reliability. Material technologies superior to Si are needed for future power device developments. Silicon Carbide (SiC) based semiconductor devices offer one such alternative. SiC based power devices exhibit superior properties such as very low switching losses, fast switching behavior, improved reliability and high temperature operation capabilities. Power factor correction stage of power supplies is identified as an area where application of these devices would prove advantageous. In this thesis a high performance, high efficiency, SiC based power factor correction stage is discussed. The proposed topology takes advantage of the superior properties of SiC semiconductor based devices and the reduced number of devices that the dual boost power factor correction topology requires to achieve high efficiency, small size and better performance at high temperature. In addition to this analysis of SiC based power devices is carried out to study their characteristics and performance.

This thesis work focuses on the study and improvement of single-stage power factor correction techniques. The generalized structures of the present pulse-width-modulation (PWM) integrated single-stage power factor correction (PFC) converters are presented. The typical PFC cells in the single-stage PFC converter are identified. After that, the necessary PFC condition is derived and verified to understand the principle of the single-stage PFC converters. As an example, the continuous current mode (CCM) current source single-stage PFC converter is studied. The circuit intuitions and design consideration of this converter are presented. Also, an improved current source single-stage PFC converter with a low-frequency auxiliary switch is proposed to overcome the problem of the previous converter. Experimental verification shows the improvement is effective. To evaluate single-stage PFC technique, a comparison study between the current source single-stage and the boost two-stage PFC converters is done in this thesis. It shows that for universal line application, due to the wide bus-capacitor voltage range, single-stage PFC converters have higher component ratings than two-stage PFC converters. This limits the application of single-stage PFC converter. Therefore, an interesting future work will be how to reduce the bus voltage range of single-stage PFC converters. / Master of Science

This dissertation presents the in-depth study and innovative solutions of the advanced integrated single-stage power-factor-correction (S2PFC) techniques, which target at the low- to medium-level power supplies, for wide range of applications, from power adapters and computers to various communication equipment. To limit the undesirable power converter input-current-harmonic's impact on the power line and other electronics equipment, stringent current harmonic regulations such as IEC 61000-3-2 have already been enforced. The S2PFC techniques have been proposed and intensively studied, in order to comply these regulations with minimal additional component count and cost. This dissertation provides a systematic study of the S2PFC input-current-shaping (ICS) mechanism, circuit topology generalization and variation, bulk capacitor voltage stress and switch current stress, converter design and optimization, and evaluation of the state-of-the-art S2PFC techniques with universal-line input. Besides, this presentation also presents the development of novel S2PFC techniques with a voltage-doubler-rectifier front end to both improve the performance and reduce the cost of S2PFC converters for (international voltage range) universal-line applications. The calculation and experimental results show that the proposed techniques offer a more cost-effective and efficient solution than industries' current practice, with universal-line input and converter power level up to 600 W. Finally, further improved technique is also presented with reduced filter inductor size and increased power density. / Ph. D.

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The traditional AC/DC rectifier usually has the defects of low power factor and serious harmonic distortion and it results in serious pollution to the power system. This thesis proposes active power factor correction technique using a new AC/DC Dual Boost Converter. For power factor correction, inductor current is operated in the continuous conduction mode. First, the converter is analyzed by state space averaging method. Furthermore, we design applicable compensator by frequency analysis to implement a good power factor system. A classical PFC circuit with PI control law has low power factor under light load. In order to overcome problem, the thesis proposes a Dual Boost Converter circuit with robust performance. Comparing with circuits using PFC IC ¡§UC3854¡¨, the proposed system obtains higher power factor under the condition of the same light load.

This thesis mainly focuses on active power factor correction (PFC) circuit research. Based on DSP, a circuit with a digital controller is developed. Boost converter is used as the power stage. For power factor correction, the control law is realized with DSP and the control strategy of controller adopts the multi-loop method, i.e. voltage-loop and modified PI current-loop. Finally, compared with the circuit using the conventional PI control law, performances of the modified PI current-loop circuit are obviously optimized.

This thesis mainly presents a LED driver circuit based on single-stage Flyback converter with power factor correction. Power factor correction technique is applied for constant current driver. Accroding to different magnetize inductance current operating mode, two methods are used to improve the drawbacks of Flyback converter which is operated in open loop. Discontinuous conduction mode is controlled by single loop which is called voltage follower control. Continuous conduction mode is controlled by dual loop, that applied to nonlinear carrier control(NLC). Multiplier is usually used to traditional power factor correction, but it is expensive. To reduce the system cost, a multiplier is removed from NLC. The designed circuit is verified by SPICE software and experiments. From simulation and experimental results, it shows the proposed system achieves the goal with high power factor and constant output current.