Two-dimensional (2D) materials have attracted extensive research interest in recent years. Among them, graphene and the semiconducting transition metal dichalcogenides (TMDs) are considered as promising candidates for future device applications due to their unique atomic thickness and outstanding properties. The study on graphene and TMDs has demonstrated great potential to further push the scaling of devices into the sub-10 nanometer regime and enable endless opportunities of novel device architectures for the next generation. In this thesis, crucial challenges facing 2D materials are investigated from material synthesis to electronic applications. A comprehensive review of the direct synthesis of graphene on arbitrary substrates with an emphasis on the metal-catalyst-free synthesis is given, followed by a detailed study of the contact engineering in TMDs with a focus on the strategies to lower the contact resistance. Effective approaches have been demonstrated to solve these issues. These include: (1) metal-catalyst-free synthesis of graphene on various insulating substrates; (2) Fermi level pinning observed in TMDs and integration of graphene contact to lower the contact resistance; and (3) application of metal-insulator-semiconductor (MIS) contact in TMD field-effect transistors (FETs). First, a direct low-temperature synthesis of graphene on insulators without any metal catalysts has been realized. The effects of carbon sources, NH3/H2 concentrations, and insulating substrates on the material synthesis have been systematically investigated. Graphene transistors based on the as-grown material have been fabricated to study the electronic properties, which can further confirm the nitrogen-doped graphene has been synthesized from the electrical characterizations. Then electronic devices focusing on the semiconducting TMDs has been studied. The Fermi level pinning has been observed and studied in WS2 FETs with four metal materials. A novel method of using graphene as an insertion layer between the metal and TMDs has been proven to effectively reduce the contact resistance. Owing to the benefit of tuning the graphene work function via the electric field, the contact resistance can further be reduced. Finally, the effectiveness of MIS contacts in WS2 FETs has been demonstrated. A thickness dependence research has been conducted to find the optimal thickness of the inserted insulator. Moreover, the possible physical mechanism of how this MIS contact reduces the contact resistance in 2D materials has been discussed.

Thesis (Ph. D.)--Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.

Thesis (M.S. in Systems Engineering)--Naval Postgraduate School, December 2003. / Thesis advisor(s): David C. Jenn, Jeffrey B. Knorr, Kevin Jones. Includes bibliographical references (p. 111-114). Also available online.

Thesis ( Ph.D. ) -- McMaster University, 1997. / Includes bibliographical references (p. 190-197) Also available via World Wide Web.

Dissertation (Ph.D.)--Auburn University, / Abstract. Vita. Includes bibliographic references (p.117-130).

Thesis (M.S. in Systems Engineering)--Naval Postgraduate School, December 2003. / "December 2003". Thesis advisor(s): David C. Jenn. Includes bibliographical references (p. 111-114). Also available online.

Thesis (Ph.D.(Physics))--University of Pretoria, 2009. / Includes abstract in English. Includes bibliographical references. Also available online.

Thesis (Ph. D.)--Ohio State University, 2005. / Title from first page of PDF file. Includes bibliographical references (p. 227-233).

Thesis (M.S.)--Rochester Institute of Technology, 2006. / Typescript. Includes bibliographical references (leaves 70-72).

The electrically active defects introduced in GaAs by electron beam deposition (EB) of Ta were characterised. The effect of electron beam deposition on the electrical properties of GaAs was evaluated by current-voltage (I-V), capacitance¬voltage (C- V) and deep level transient spectroscopy (DL TS). However, when electronic devices are formed by EB, defects may be introduced into the semiconductor material, depending on the properties of the metal being deposited. Depending on the application, these defects may have either advantages or detrimental effects on the performance of such a device. I-V measurements indicated that the EB induced damage results in an increase in ideality factor and decrease in the barrier height with increasing the applied substrate bias, while C- V measurements showed that EB deposition also caused a decrease in the barrier height. DL TS studies on the same material in the temperature range of 20 - 350 K showed that at least three electrically active defects are introduced during EB deposition, with energies (0.102 ± 0.004, 0.322 ± 0.014 and 0.637 ± 0.029 eV) within the band gap. DL TS data was used to construct concentration profiles of these defects as a function of depth below the surface. It was found that the defect concentration increases with increasing substrate bias during the deposition, irrespective of the direction of the applied bias. This may be related to the I-V characteristics of the SBDs. The SBDs investigated by IV measurements showed that GaAs yields SBDs with poorer characteristic. The influence of EB deposition on the device properties of SBDs fabricated on GaAs is presented. These device properties were monitored using a variable temperature I-V and C- V apparatus. In order to have an understanding of the change in electrical properties of these contacts after EB deposition, it is necessary to characterise the EB induced defects. DL TS was used to characterise the defects in terms of their D L TS signature and defect concentration. / Dissertation (MSc (Physics))--University of Pretoria, 2006. / Physics / unrestricted