The continuous and aggressive downscaling of conventional CMOS devices has been driving the vast growth of ICs over the last few decades. As the CMOS downscaling approaches the fundamental limits, novel device architectures such as metallic source/drain Schottky barrier MOSFET (SB-MOSFET) and SB-FinFET are probably needed to further push the ultimate downscaling. The ultimate goal of this thesis is to integrate metallic Ni1-xPtx silicide (x=0~1) source/drain into SB-MOSFET and SB-FinFET, with an emphasis on both material and processing issues related to the integration of Ni1-xPtx silicides towards competitive devices. First, the effects of both carbon (C) and nitrogen (N) on the formation and on the Schottky barrier height (SBH) of NiSi are studied. The presence of both C and N is found to improve the poor thermal stability of NiSi significantly. The present work also explores dopant segregation (DS) using B and As for the NiSi/Si contact system. The effects of C and N implantation into the Si substrate prior to the NiSi formation are examined, and it is found that the presence of C yields positive effects in helping reduce the effective SBH to 0.1-0.2 eV for both conduction polarities. In order to unveil the mechanism of SBH tuning by DS, the variation of specific contact resistivity between silicide and Si substrates by DS is monitored. The formation of a thin interfacial dipole layer at silicide/Si interface is confirmed to be the reason of SBH modification. Second, a systematic experimental study is performed for Ni1-xPtx silicide (x=0~1) films aiming at the integration into SB-MOSFET. A distinct behavior is found for the formation of Ni silicide films. Epitaxially aligned NiSi2-y films readily grow and exhibit extraordinary morphological stability up to 800 oC when the thickness of deposited Ni (tNi) <4 nm. Polycrystalline NiSi films form and tend to agglomerate at lower temperatures for thinner films for tNi≥4 nm. Such a distinct annealing behavior is absent for the formation of Pt silicide films with all thicknesses of deposited Pt. The addition of Pt into Ni supports the above observations. Surface energy is discussed as the cause responsible for the distinct behavior in phase formation and morphological stability. Finally, three different Ni-SALICIDE schemes towards a controllable NiSi-based metallic source/drain process without severe lateral encroachment of NiSi are carried out. All of them are found to be effective in controlling the lateral encroachment. Combined with DS technology, both n- and p-types of NiSi source/drain SB-MOSFETs with excellent performance are fabricated successfully. By using the reproducible sidewall transfer lithography (STL) technology developed at KTH, PtSi source/drain SB-FinFET is also realized in this thesis. With As DS, the characteristics of PtSi source/drain SB-FinFET are transformed from p-type to n-type. This thesis work places Ni1-xPtx (x=0~1) silicides SB-MOSFETs as a competitive candidate for future CMOS technology. / QC20100708 / NEMO, NANOSIL, SINANO

<p>Silicon carbide is a promising wide bandgap semiconductormaterial for high-temperature, high-power, and high-frequencydevice applications. However, there are still a number offactors that are limiting the device performance. Among them,one of the most important and critical factors is the formationof low resistivity Ohmic contacts and high-temperature stableSchottky diodes on silicon carbide.</p><p>In this thesis, different metals (TiW, Ti, TiC, Al, and Ni)and different deposition techniques (sputtering andevaporation) were suggested and investigated for this purpose.Both electrical and material characterizations were performedusing various techniques, such as I-V, C-V, RBS, XRD, XPS,LEED, SEM, AFM, and SIMS.</p><p>For the Schottky contacts to n- and p-type 4H-SiC, sputteredTiW Schottky contacts had excellent rectifying behavior afterannealing at 500 ºC in vacuum with a thermally stableideality factor of 1.06 and 1.08 for n- and p-type,respectively. It was also observed that the SBH for p-type SiC(Φ_Bp) strongly depends on the choice the metal with alinear relationship Φ_Bp= 4.51 - 0.58Φ_m, indicating no strong Fermi-level pinning.Finally, the behavior of Schottky diodes was investigated byincorporation of size-selected Au nano-particles in Ti Schottkycontacts on silicon carbide. The reduction of the SBH isexplained by using a simple dipole layer approach, withenhanced electric field at the interface due to the small sizeof the circular patch (Au nano-particles) and large differenceof the barrier height between two metals (Ti and Au) on both n-and p-SiC.</p><p>For the Ohmic contacts, titanium carbide (TiC) was used ascontacts to both n- and p-type 4H-SiC epilayers as well as onAl implanted layers. The TiC contacts were epitaxiallydeposited using a co-evaporation method with an e-beam Tisource and a Knudsen cell for C₆₀, in a UHV system at low substrate temperature(500 ºC). In addition, we extensively investigatedsputtered TiW (weight ratio 30:70) as well as evaporated NiOhmic contacts on both n- and p-type epilayers of SiC. The bestOhmic contacts to n-type SiC are annealed Ni (>950ºC)with the specific contact resistance of ≈ 8× 10^-6Ω cm²with doping concentration of 1.1 × 10^-19cm^-3while annealed TiW and TiC contacts are thepreferred contacts to p-type SiC. From long-term reliabilitytests at high temperature (500 ºC or 600 ºC) invacuum and oxidizing (20% O₂/N₂) ambient, TiW contacts with a platinum cappinglayer (Pt/Ti/TiW) had stable specific contact resistances for>300 hours.</p><p><b>Keywords</b>: silicon carbide, Ohmic and Schottky contacts,co-evaporation, current-voltage, capacitance-voltagemeasurement, power devices, nano-particles, Schottky barrierheight lowering, and TLM structures.</p>

Thesis (Ph. D.)--Ohio State University, 2006. / Title from first page of PDF file. Includes bibliographical references (p. 191-206).

Made available in DSpace on 2015-03-26T13:35:16Z (GMT). No. of bitstreams: 1 texto completo.pdf: 3403324 bytes, checksum: 2828289d9a42c60c7cb3b860cb3dca61 (MD5) Previous issue date: 2011-05-30 / Conselho Nacional de Desenvolvimento Científico e Tecnológico / In this work the techniques of hot wall epitaxy (HWE) and molecular beam epitaxy (MBE) on thin films of CdTe (cadmium telluride) were used in order to manufacture a prototype solar cell type Schottky barrier. The films were produced by evaporation of a solid alloy of CdTe, varying two parameters of deposition: the growth time and substrate temperature. In the manufacture the Schottky Barrier solar cells Al-CdTe, the CdTe film was grown on glass substrate coated with a layer of TO (tin oxide doped with fluorine - SnO2:F) and an evaporation system was used in the deposition of Al contacts. The films were characterized by several techniques including profilometry to measure the thickness, atomic force microscopy (AFM) for determining surface morphology and x-ray diffraction for crystalline properties. The prototypes of the solar cell were characterized by electrical measurements (IxV curve) with and without illumination. The results show a strong influence of substrate temperature and thickness on the properties of solar cells. It was observed that the increase of substrate temperature favors the increase of grain and the growth of films with better quality, resulting in devices with better features. In addition, thinner layers of CdTe cells also produce a higher short circuit current when illuminated. Although the cells produced showed very low efficiency, we believe that it is possible to improve manufacturing processes, achieving better efficiency. / Neste trabalho utilizou-se as técnicas de epitaxia por paredes quentes (HWE) e epitaxia por feixe molecular (MBE) na fabricação de filmes finos de CdTe (telureto de cádmio) com o objetivo de fabricar um protótipo de célula solar tipo barreira Schottky. Os filmes foram obtidos por evaporação de uma liga sólida de CdTe, fazendo-se variar dois parâmetros de deposição: o tempo de crescimento e a temperatura do substrato. Na fabricação das células solares tipo Barreira Schottky Al-CdTe, o filme de CdTe foi crescido sobre o substrato de vidro recoberto com uma camada de TO (óxido de estanho dopado com Flúor &#8211; SnO2:F) e uma metalizadora foi utilizada na deposição dos contatos de Al. Os filmes foram caracterizados por diversas técnicas, incluindo a perfilometria para medida da espessura, a microscopia de força atômica (AFM) para determinação das propriedades morfológicas e difração de raios-x para determinação das propriedades cristalinas. Os protótipos da célula solar foram caracterizados através de medidas elétricas da curva IxV com e sem iluminação. Os resultados obtidos mostram uma forte influência da temperatura do substrato e da espessura nas propriedades das células solares construídas. Observou-se que o aumento da temperatura do substrato favorece o aumento do grão e o crescimento de filmes com melhor qualidade resultando em dispositivos com melhores características. Além disso, camadas mais finas de CdTe também produzem células que apresentam maior corrente de curto-circuito, quando iluminadas. Apesar das células fabricadas apresentarem eficiência muita baixa, acreditamos que existe a possibilidade de melhorar os processos de fabricação, conseguindo melhorar a eficiência.

Táto práca sa zaoberá technikou výroby samousporiadaných nanoštruktúr pre elektrické aplikácie. Prototypy boli pripravené anodickou oxidáciou v dvoch dĺžkach a tromi rôznymi tepelnými úpravami. Štrukturálna charakterizácia bola spravená pomocou techniky SEM, TEM a EDX a vyhodnotenie nielen z štrukturálneho, ale aj z materiálového hľadiska. Jedinečná koreňová štruktúra samousporiadaných nanotyčiniek bola vyhodnotená a porovnaná po troch rôznych tepelných úpravách: po anodizácii, po vákuovom žíhaní, a po žíhaní vo vzduchu. Všetky prototypy obsahujú nanotyčinky s amorfnou štruktúrou, ale našli sa však aj nanokryštály pod koreňovými štruktúrami. Elektrická charakterizácia prototypov ukázala: odporové spínacie správanie (RS), diódové charakteristiky a charakteristiku podobnú pre diódy s kapacitorom. Aktívny povrch pre spínací mechanizmus je v hornej časti nanoštruktúr na rozhraní nanotyčiniek a zlatej elektródy. Výška Schottkyho bariéry na rozhraní Ti / TiO2 bola vypočítaná dvoma spôsobmi a pre všetky tri zariadenia bola nižšia ako 1,11 eV.

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Cette thèse se place dans le cadre du projet Diamonix, qui vise à établir une filière diamant en France. La thèse porte sur des travaux de dimensionnement de protection périphérique, structure nécessaire au bon fonctionnement des composants d’électronique de puissance. Le développement de protections périphériques applicables aux diodes Schottky sur diamant monocristallin nécessite plusieurs étapes. Après un premier chapitre détaillant l’état de l’art de l’utilisation de diamant en électronique de puissance, nous nous attardons sur la conception de protection périphérique basée sur une plaque de champ à l’aide de divers diélectriques et ensuite à l’aide d’un matériau semi-résistif dans le chapitre 2. Ces simulations sont réalisées à l’aide du logiciel SENTAURUS TCAD. Le troisième chapitre essaie de répondre aux problèmes technologiques posés par le chapitre 2. Nous avons ainsi développé une nouvelle technique de gravure basée sur une succession d’étapes utilisant Ar/O2 puis CF4/O2. Puis, dans un deuxième temps, nous avons réalisé des capacités Métal/Diélectrique/Diamant afin de qualifier le comportement des diélectriques sur le matériau diamant. Leur comportement est problématique mais il s’agit à notre connaissance de la première étude poussée de capacités sur diamant. Le chapitre 4 revient sur la fabrication et la caractérisation de diodes Schottky protégées à l’aide de plaques de champ sur divers diélectriques, les résultats obtenus étant mitigés. Enfin, la conclusion revient sur les résultats importants de simulation, de gravure, de caractérisation des capacités et des diodes Schottky pour ensuite s’élargir et donner des perspectives de travail. / This thesis work is part of the Diamonix project, which is about forming a France-based supply and fabrication of diamond electronics devices. Work in this thesis is centered upon designing a peripheral junction protection suitable for diamond Schottky diodes, a vital structure for the right behavior of power electronics components. Such design on monocristalline diamond substrates needs several steps. After a first chapter dealing with diamond state of the art in power electronics, emphasis is brought upon the design of a field plate protection using several dielectric materials and a semi-resistive component in the second chapter. Those simulations are carried out using SENTAURUS TCAD software suite. The third chapter tries to answer any technological difficulties met in the second chapter. For instance, a new etching technique based upon a succession of steps has beeen developped. Then, Metal/Dielectric/Diamond capacitors were made to determine the electrical behavior of those dielectrics on diamond. Their behavior is problematic but it is to our knowledge the first time such devices are characterized in such extent. The fourth chapter deals with the processing and characterizing of diamond Schottky diodes protected using field plates on several dielectrics, which measurements results are a bit disappointing. Finally, the conclusion insists on the main results of the thesis and then opens up to a discussion over the perspectives of future works around diamond.

This thesis investigates the possibility of enhancing the efficiency of thin film solar cells by including periodic material nonhomogeneities in combination with periodically corrugated back reflectors. Two different types of solar cell are investigated; p-i-n junctions solar cells made from alloys of hydrogenated amorphous silicon (a-Si:H) (containing either carbon or germanium), and Schottky barrier junction solar cells made from alloys of indium gallium nitride (InξGa1-ξN). Material nonhomogeneities are produced by varying the fractions of the constituent elements of the alloys. For example, by varying the content of carbon or germanium in the a-Si:H alloys, semiconductors with bandgaps ranging from 1:3 eV to 1:95 eV can be produced. Changing the bandgap alters both the optical and electrical properties of the material so this necessitates the use of coupled optical and electrical models. To date, the majority of solar cell simulations either prioritise the electrical portion of the simulation or they prioritise the optical portion of the simulation. In this thesis, a coupled optoelectronic model, developed using COMSOL Multiphysics®, was used to simulate solar cells: a two-dimensional finite-element optical model, which solved Maxwell's equations throughout the solar cells, was used to calculate the absorption of incident sunlight; and a finite-element electrical drift-diffusion transport model, either one- or two-dimensional depending on the symmetries of the problem, was used to calculate the steady state current densities throughout the solar cells under external voltage biases. It is shown that a periodically corrugated back reflector made from silver can increase efficiency of an a-Si:H alloy single p-i-n junction solar cell by 9:9% compared to a baseline design, while for a triple junction the improvement is a relatively meagre 1:8%. It is subsequently shown that the efficiency of these single p-i-n junction solar cells with a back reflector can be further increased by the inclusion of material nonhomogeneities, and that increasing the nonhomogeneity progressively increases efficiency, especially in thicker solar cells. In the case of InξGa1-ξN Schottky barrier junction solar cells, the gains are shown to be even greater. An overall increase in efficiency of up to 26:8% over a baseline design is reported.

The steady and aggressive downscaling of the physical dimensions of the conventional metal-oxide-semiconductor field-effect-transistor (MOSFET) has been the main driving force for the IC industry and information technology over the past decades. As the device dimensions approach the fundamental limits, novel double/trigate device architecture such as FinFET is needed to guarantee the ultimate downscaling. Furthermore, Schottky barrier source/drain technology presents a promising solution to reducing the parasitic source/drain resistance in the FinFET. The ultimate goal of this thesis is to integrate Schottky barrier source/drain in FinFETs, with an emphasis on process development and integration towards competitive devices. First, a robust sidewall transfer lithography (STL) technology is developed for mass fabrication of Si-nanowires in a controllable manner. A scalable self-aligned silicide (SALICIDE) process for Pt-silicides is also developed. Directly accessible and uniform NWs of Ni- and Pt-silicides are routinely fabricated by combining STL and SALICIDE. The silicide NWs are characterized by resistivity values comparable to those of their thin–film counterparts. Second, a systematic experimental study is performed for dopant segregation (DS) at the PtSi/Si and NiSi/Si interfaces in order to modulate the effective SBHs needed for competitive FinFETs. Two complementary schemes SIDS (silicidation induced dopant segregation) and SADS (silicide as diffusion source) are compared, and both yield substantial SBH modifications for both polarities of Schottky diodes (i.e. φbn and φbp). Third, Schottky barrier source/drain MOSFETs are fabricated in UTB-SOI. With PtSi that is usually used as the Schottky barrier source/drain for p-channel SB-MOSFETs, DS with appropriate dopants leads to excellent performance for both types of SBMOSFETs. However, a large variation in position of the PtSi/Si interface with reference to the gate edge (i.e., underlap) along the gate width is evidenced by TEM. Finally, integration of PtSi NWs in FinFETs is carried out by combining the STL technology, the Pt-SALICIDE process and the DS technology, all developed during the course of this thesis work. The performance of the p-channel FinFETs is improved by DS with B, confirming the SB-FinFET concept despite device performance fluctuations mostly likely due to the presence of the PtSi-to-gate underlap. / QC 20100923