Silicon carbide (SiC) has higher breakdown field strength than silicon (Si), which enables thinner and more highly doped drift layers compared to Si. Consequently, the power losses can be reduced compared to Si-based power conversion systems. Moreover, SiC allows the power conversion systems to operate at high temperatures up to 250 oC. With such expectations, SiC is considered as the material of choice for modern power semiconductor devices for high efficiencies, high temperatures, and high power densities. Besides the material benefits, the typeof the power device also plays an important role in determining the system performance. Compared to the SiC metal-oxide semiconductor field-effect transistor (MOSFET) and bipolar junction transistor (BJT), the SiC junction field-effect transistor (JFET) is a very promising power switch, being a voltage-controlled device without oxide reliability issues. Its channel iscontrolled by a p-n junction. However, the present JFETs are not optimized yet with regard to on-state resistance, controllability of threshold voltage, and Miller capacitance. In this thesis, the state-of-the-art SiC JFETs are introduced with buried-grid (BG) technology.The buried grid is formed in the channel through epitaxial growth and etching processes. Through simulation studies, the new concepts of normally-on and -off BG JFETs with 1200 V blocking capability are investigated in terms of static and dynamic characteristics. Additionally, two case studies are performed in order to evaluate total losses on the system level. These investigations can be provided to a power circuit designer for fully exploiting the benefit of power devices. Additionally, they can serve as accurate device models and guidelines considering the switching performance. The BG concept utilized for JFETs has been also used for further development of SiC junctionbarrier Schottky (JBS) diodes. Especially, this design concept gives a great impact on high temperature operation due to efficient shielding of the Schottky interface from high electric fields. By means of simulations, the device structures with implanted and epitaxial p-grid formations, respectively, are compared regarding threshold voltage, blocking voltage, and maximum electric field at the Schottky interface. The results show that the device with an epitaxial grid can be more efficient at high temperatures than that with an implanted grid. To realize this concept, the device with implanted grid was optimized using simulations, fabricated and verified through experiments. The BG JBS diode clearly shows that the leakage current is four orders of magnitude lower than that of a pure Schottky diode at an operation temperature of 175 oC and 2 to 3 orders of magnitude lower than that of commercial JBS diodes. Finally, commercialized vertical trench JFETs are evaluated both in simulations andexperiments, while it is important to determine the limits of the existing JFETs and study their performance in parallel operation. Especially, the influence of uncertain parameters of the devices and the circuit configuration on the switching performance are determined through simulations and experiments. / Kiselkarbid (SiC) har en högre genombrottsfältstyrka än kisel, vilket möjliggör tunnare och mer högdopade driftområden jämfört med kisel. Följaktligen kan förlusterna reduceras jämfört med kiselbaserade omvandlarsystem. Dessutom tillåter SiC drift vid temperatures upp till 250 oC. Dessa utsikter gör att SiC anses vara halvledarmaterialet för moderna effekthalvledarkomponenter för hög verkningsgrad, hög temperature och hög kompakthet. Förutom materialegenskaperna är också komponenttypen avgörande för att bestämma systemets prestanda. Jämfört med SiC MOSFETen och bipolärtransistorn i SiC är SiC JFETen en mycket lovande component, eftersom den är spänningsstyrd och saknar tillförlitlighetsproblem med oxidskikt. Dess kanal styrs an en PNövergång. Emellertid är dagens JFETar inte optimerade med hänseende till on-state resistans, styrbarhet av tröskelspänning och Miller-kapacitans. I denna avhandling introduceras state-of-the-art SiC JFETar med buried-grid (BG) teknologi. Denna åstadkommes genom epitaxi och etsningsprocesser. Medelst simulering undersöks nya concept för normally-on och normally-off BG JFETar med blockspänningen 1200 V. Såvä statiska som dynamiska egenskper undersöks. Dessutom görs två fallstudier vad avser totalförluster på systemnivå. Dessa undersökningar kan vara värdefulla för en konstruktör för att till fullo utnyttja fördelarna av komponenterna. Dessutom kan resultaten från undersökningarna användas som komponentmodeller och anvisningar vad gäller switch-egenskaper. BG konceptet som använts för JFETar har också använts för vidareutveckling av så kallade JBS-dioder. Speciellt ger denna konstruktion stora fördelar vid höga temperature genom en effektiv skärmning av Schottkyövergången mot höga elektriska fält. Genom simuleringar har komponentstrukturer med implanterade och epitaxiella grids jämförst med hänseende till tröskelspänning, genombrottspänning och maximalt elektriskt fält vid Schottky-övergången. Resultaten visar att den epitaxiella varianten kan vara mer effektiv än den implanterade vid höga temperaturer. För att realisera detta concept optimerades en komponent med implanterat grid med hjälp av simuleringar. Denna component tillverkades sedan och verifierades genom experiment. BG JBS-dioden visar tydligt att läckströmmen är fyra storleksordningar lägre än för en ren Schottky-diod vid 175 oC, och två till tre storleksordningar lägre än för kommersiella JBS-dioder. Slutligen utvärderas kommersiella vertical trench-JFETar bade genom simuleringar och experiment, eftersom det är viktigt att bestämma gränserna för existerande JFETar och studera parallelkoppling. Speciellt studeras inverkan av obestämda parametrar och kretsens konfigurering på switchegenskaperna. Arbetet utförs bade genom simuleringar och experiment. / <p>QC 20150915</p>

As scaling of CMOS technology continues, the control of parasitic source/drain (S/D) resistance (RSD) is becoming increasingly challenging. In order to control RSD, metallic source/drain MOSFETs have attracted significant attention, due to their low resistivity, abrupt junction and low temperature processing (≤700 °C). A key issue is reducing the contact resistance between metal and channel, since small Schottky barrier height (SBH) is needed to outperform doped S/D devices. A promising method to decrease the effective barrier height is dopant segregation (DS). In this work several relevant aspects of Schottky barrier (SB) contacts are investigated, both by simulation and experiment, with the goal of improving performance and understanding of SB-MOSFET technology:First, measurements of low contact resistivity are challenging, since systematic error correction is needed for extraction. In this thesis, a method is presented to determine the accuracy of extracted contact resistivity due to propagation of random measurement error.Second, using Schottky diodes, the effect of dopant segregation of beryllium (Be), bismuth (Bi), and tellurium (Te) on the SBH of NiSi is demonstrated. Further study of Be is used to analyze the mechanism of Schottky barrier lowering.Third, in order to fabricate short gate length MOSFETs, the sidewall transfer lithography process was optimized for achieving low sidewall roughness lines down to 15 nm. Ultra-thin-body (UTB) and tri-gate SB-MOSFET using PtSi S/D and As DS were demonstrated. A simulation study was conducted showing DS can be modeled by a combination of barrier lowering and doped Si extension.Finally, a new Schottky contact model was implemented in a multi-subband Monte Carlo simulator for the first time, and was used to compare doped-S/D to SB-S/D for a 17 nm gate length double gate MOSFET. The results show that a barrier of ≤ 0.15 eV is needed to comply with the specifications given by the International Technology Roadmap for Semiconductors (ITRS). / QC 20111206

Thesis (Ph. D.)--Ohio State University, 2006. / Title from first page of PDF file. Includes bibliographical references (p. 209-217).

The physical and chemical properties of In- and Au- interfaces with In[0.53]Ga[0.47]As/InP(100) and In[0.52]Al[0.48]As(100) formed at room and low temperatures have been studied. Current-voltage measurements have indicated that In contacts to Ino[0.53]Ga[0.47]As(100) formed at 80K exhibit significantly higher Schottky barriers (&phis;b=0.45 eV) than In diodes formed at 294K (&phis;b=0.30 eV), whereas Au diodes formed on In[0.53]Ga[0.47]As(100) at either low temperature or room temperature exhibit Ohmic behaviour. The reactions occurring during interface formation at room and low temperatures have been investigated using soft X-ray photoemission spectroscopy (SXPS) and Transmission Electron Microscopy (TEM).The results presented show that In metallisation of In[0.53]Ga[0.47]As(100) at room temperature results in a predominantly three dimensional mode of growth, accompanied by the out-diffusion of As. Low temperature (125K) metallisation appears to reduce clustering and inhibit As out-diffusion. Examination of the resulting interfaces by TEM confirm the more uniform nature of the metal layers formed at low temperature. Metallisation temperature seems to have little effect on the formation of Au-In[0.53]Ga[0.47]As(100) interfaces, other than to reduce the extent of overlayer clustering, with As out-diffusion apparent for both low and room temperature Au deposition. Interfaces formed between In and In[0.52]Al[0.48]As(100) at both low and room temperature were relatively abrupt with no out-diffusion of substrate species into the metal overlayer. Low temperature metallisation again appeared to reduce overlayer clustering, with TEM studies showing a smaller grain size at low temperature. Au deposition onto In[0.52]Al[0.48]As(100) produced similar interfaces formed at room and low temperature. As diffuses into the Au overlayer to form an Au/As compound at both temperatures, resulting in an interface that is complex and reacted. The degree of overlayer clustering is also thought to be much less pronounced for Au deposition compared to In deposition. Barrier heights measured by SXPS during the study, show good agreement with reported current-voltage measurements for Au and In diodes formed on both In[0.53]Ga[0.47]As/InP(100) and In[0.52]Al[0.48]As(100). Possible mechanisms for the observed adaptation of the pinning position are discussed in the context of current models of Schottky barrier formation.

La conception, fabrication et caractérisation d’un récepteur hétérodyne à 1.2 THz a été effectuée par le Laboratoire d’Etudes du Rayonnement et de la Matière en Astrophysique et Atmosphères (LERMA) et constitue la base de ce rapport de thèse. Les études, analyse et résultats présentés dans ce manuscrit ont été effectués dans le cadre la mission JUpiter ICe moon Explorer (JUICE). JUICE est la première des grandes missions proposées à l’agenda du programme spatial Cosmic Vision 2015-2025 de l’Agence Spatial Européenne (ESA). La mission satellitaire JUICE est consacrée à l’étude du système Jovien. La charge utile du satellite est composée de 10 instruments à l’état-de-l’art et d'une expérience. Le développement du récepteur hétérodyne à 1.2 THz présenté dans cette thèse est dédié à SWI, acronyme anglais de “Submillimeter Wave Instrument", qui, grâce à une résolution spectrale de 107, étudiera à partir de 2030 la structure, la composition et la dynamique des températures de la stratosphère et de la troposphère de Jupiter ainsi que les exosphères et les surfaces des lunes glacées. La partie haute fréquence du récepteur est complètement basée sur la technologie de diodes Schottky planaires sur membrane d'arséniure de galium (GaAs), appelées “Planar Schottky Barrier Diodes” (PSBDs) dans le manuscrit. La réalisation du canal à 1.2 THz de SWI basé sur la technologie Schottky et entièrement développé par le consortium européen, dont fait parti le LERMA, a été le défi le plus significatif rencontré par ce dernier. L'extrême réduction de la taille des anodes des diodes Schottky nécessaire pour monter aux fréquences du THz a été atteinte en collaboration avec le Laboratoire de Photonique et de Nanostructures (LPN) en utilisant la lithographie électronique pour la fabrication de véritables “Monolithic Microwave Integrated Circuits” (MMIC).Une partie importante du ce rapport de thèse et consacrée à l’étude des phénomènes physiques additionnels qui apparaissent quand les dimensions des diodes sont fortement réduites. En particulier, les modifications du comportement résistif et capacitif des diodes Schottky dues à des phénomènes microscopiques bidimensionnels ont été étudiées au moyen d’un simulateur bidimensionnel Monte Carlo (2D-MC), en collaboration avec l’Université de Salamanca, en Espagne.Comme détaillé dans ce manuscrit, la caractérisation précise du comportement capacitif de la diode Schottky est un point critique pour déterminer la plage de fréquences de leur utilisation pour une application donnée. Toute modélisation imprécise de cette propriété de la diode peut entrainer un décalage significatif de la plage de fréquences d’opération d'un circuit THz.Cependant, la modélisation précise des diodes Schottky à ultra-hautes fréquences, n'est qu'une des étapes requises pour réussir à concevoir correctement un circuit THz. L’analyse précise et méticuleuse de l’interaction entre le comportement électromagnétique du chip MMIC et le comportement physique des diodes Schottky a été le but le plus important poursuit dans ce travail doctoral pour le développement du récepteur à 1.2 THz. Cette tâche a été abordée en utilisant les outils commerciaux “High Frequency Simulation/Structure Software” (Ansys-HFSS) et “Keysight Advance Design System” (Keysight-ADS). La combinaison des simulations électromagnétiques des structures tridimensionnelles du chip MMIC (Ansys-HFSS) et les simulations du comportement électrique non-linéaire de la diode Schottky (Keysight-ADS) est la manière actuelle d'aborder la conception de ce type de circuits THz. Le modèle électrique analytique de la diode requis par l’outil ADS a été défini par l'auteur conformément aux résultats précédemment obtenus avec le simulateur physique Monte Carlo. L’implémentation du modèle étendu de la diode Schottky dans cette méthode pour la conception et l'optimisation de chaque étage du récepteur à 1.2THz, est le sujet développé dans ce rapport de thèse. / The design, fabrication and testing of a frequency heterodyne receiver at 1.2 THz has been developed by Laboratoire d’Etudes du Rayonnement et de la Matière en Astrophysique et Atmosphères (LERMA) and it is the foundation of this dissertation. The studies, analysis and results presented in this manuscript have been carried out within the framework of the JUpiter ICe moon Explorer (JUICE) mission. JUICE is one of the proposed missions in the agenda of the European Space Agency (ESA) Cosmic Vision 2015-2025 program. The objective of the JUICE satellite mission is to study the Jovian system, especially the Jupiter atmosphere properties and the surface characteristics of its icy moons. Scientific equipment consisting of ten state-of-the-art instruments and one experiment comprise the payload of this satellite. The development of a 1.2 THz channel is part of the Submillimeter Wave Instrument (SWI) devoted to recovering the spectroscopy data of the Jupiter atmosphere and icy-moons’ surface composition. The scientific principle for this receiver is all-solid-state semiconductor technology based in GaAs Planar Schottky Barrier Diodes (PSBDs). The achievement of a 1.2 THz channel based in PSBDs totally developed by European partners was the major challenge proposed for SWI, with LERMA committed to this assignment. The required ultra-scaling of the Schottky anode size of PSBDs in the attainment of the THz range has been achieved in collaboration with Laboratoire de Photonique et de Nanostructures (LPN) using e-beam photolithography in the fabrication of Monolithic Microwave Integrated Circuits (MMIC). An important part of this dissertation addresses the appearance of additional physical phenomena when ultrascaling solid-state PSBDs. Particularly, the modification of the electrical resistivity and capacitance of SBDs due to two-dimensional phenomena has been studied by means of a physical microscopic Two-Dimensional Monte Carlo (2D-MC) simulator, in collaboration with the University of Salamanca, Salamanca, Spain. As discussed within this manuscript, the accurate characterization of the diode capacitance is one of the critical points when opening a frequency window in the required frequency range of a THz application. A misunderstanding of this modified capacitance during the design of these devices can lead to a considerable offset in the frequency range of the experimental module. However, the accurate modeling of PSBDs in such high frequency applications is only a part of the expertise required for the successful completion of this challenge. The accurate and meticulous analysis of the interrelationship between the electromagnetic behavior of the MMIC chip and the physical behavior of the integrated PSBDs is the main challenge faced in this dissertation for the development of the 1.2 THz receiver. This task has been addressed using the commercial Ansys High Frequency Simulation/Structure Software (Ansys-HFSS) and the Keysight Advance Design System (Keysight-ADS). The combination of the three-dimensional electromagnetic characterization of the chip structure (obtained with HFSS) with the non-linear electrical circuit simulation (carried out by ADS) of diodes is the current methodology for the design of these modules. The analytical electrical model of PSBDs required by ADS software has been defined by this author in agreement with the results obtained with the 2D-MC simulator. The implementation of this approach in the design and optimization of the different stages of the accomplished 1.2 THz receiver is the main subject of this dissertation. The interaction between the physical model of the PSBDs and the electromagnetic modeling of the structure will be discussed within the different chapters of this dissertation. Finally, the mechanical engineering of these applications must be addressed in this discussion.

L'introduction de la supraconductivité dans des structures de type MOSFET en silicium ouvre de nouvelles perspectives dans la recherche en physique. Dans cette thèse, on s'intéresse aux propriétés de transport électronique au sein d'un MOSFET fabriqué avec des sources et drains supraconducteurs. Afin de garantir la reproductibilité de ces dispositifs, il est important d'intégrer des matériaux supraconducteurs compatibles avec la technologie CMOS exploitant la technologie silicium qui a pour énorme avantage d'être véritablement fiable et mature. L'idée fondamentale est de réaliser un nouveau type de circuit supraconducteur avec une géométrie de type transistor dans lequel un supracourant non dissipatif circulant au sein du dispositif, de la source vers le drain, serait modulé par une tension de grille : un JOFET. Une perspective importante est la réalisation d'un qubit supraconducteur grâce à une technologie parfaitement reproductible et mature. Cependant, à très basse température et avec la diminution de la taille des dispositifs, deux phénomènes a priori antagonistes entrent en compétition, à savoir la supraconductivité qui implique un grand nombre d'électrons condensés dans le même état quantique macroscopique et l'interaction Coulombienne qui décrit des processus de transport à une particule. L'intérêt de l'étude est donc de réaliser de tels transistors afin de mieux comprendre comment ce genre de dispositif hybride peut s'adapter à des propriétés opposées. Dans cette thèse, j'ai étudié deux façons d'introduire la supraconductivité dans nos dispositifs. La première option est de réaliser des sources et drains en silicium rendus supraconducteurs par dopage en bore et recuit laser effectué grâce à des techniques de dopage hors-équilibre robustes et bien maîtrisées. Même si la supraconductivité du silicium très fortement dopé en bore est connue depuis 2006 et son état supraconducteur a été très bien caractérisé sur des couches bidimensionnelles, la supraconductivité du SOI, qui est le substrat initial à la base de certains transistors, n'a jamais encore été testée et étudiée. L'objectif est de pouvoir adapter ces techniques de dopage au SOI afin de le rendre supraconducteur et de pouvoir l'intégrer par la suite dans des dispositifs de type MOSFET. La seconde option considérée est la réalisation de source et drain à base de siliciures supraconducteurs tel que le PtSi. Ce siliciure est intéressant du point de vue de sa température critique relativement haute de 1K. D'un point de vue technologique, les MOSFETs à barrière Schottky présentant des contacts en PtSi supraconducteur ont été élaborés au CEA/LETI. Les mesures à très basse température au sein d'un cryostat à dilution ont mis en évidence cette compétition entre la supraconductivité et les effets d'interaction Coulombienne et ont également révélé la supraconductivité dans le MOSFET comportant des contacts en PtSi grâce notamment à l'observation du gap induit dans le dispositif. / Superconducting transport through a silicon MOSFET can open up many new possibilities ranging from fundamental research to industrial applications. In this thesis, we investigate the electric transport properties of a MOSFET built with superconducting source and drain contacts. Due to their advantages in terms of scalability and reproducibility, we want to integrate superconducting materials compatible with CMOS technology, thus exploiting the reliable and mature silicon technology. The idea is to realize a new type of superconducting circuits in a transistor geometry in which a non-dissipative supercurrent flowing through the device from source to drain will be modulated by a gate: a JOFET. One important outcome is the realization of superconducting qubits in a perfectly reproducible and mature technology. However, at low temperature and with the reduction of the size of the devices, two antagonistic phenomena appear. The dissipation-free transport of Cooper pairs competes with lossy single-particle processes due to Coulomb interactions. The goal is to understand how these two conflicting properties manifest in such hybrid devices. In this thesis, I studied two different ways of introducing superconductivity in the devices. We deployed a high boron doping and a laser annealing provided by well-controlled out-of-equilibrium doping techniques to make the silicon superconducting. Although highly boron-doped silicon has been known to be superconducting since 2006, superconductivity of SOI, the basic brick of some transistors, was never tested before. We aim at adapting those doping techniques on SOI in order to make it superconducting and to integrate it in transistor-like devices. In a second project, we study source and drain contacts fabricated with superconducting silicides such as PtSi. Such Schottky barrier MOSFETs with superconducting PtSi contacts are elaborated at the CEA/LETI. Measurements at very low temperature revealed the competition between superconductivity and Coulomb interactions and moreover, have brought evidence of superconductivity in PtSi based silicon Schottky barrier MOSFET.

Afin de permettre de développer un modèle de mémoire non-volatile basée sur le transistor à nanotube de carbone à commande optique qui est utilisée dans des circuits électroniques neuromorphiques, il est nécessaire de comprendre les physiques électroniques et optoélectroniques des nanotubes de carbone, en particulier l’origine de l'effet mémoire que présente ces transistors. C’est dans ce contexte général que cette thèse s'intègre. Le travail est mené sur trois plans :• Caractériser électriquement et optoélectroniquement des structures de test des CNTFETs et des OG-CNTFETs.• Développer un modèle compact pour les contacts Schottky dans les transistors à nanotube de carbone de la façon auto-cohérente basé sur le diamètre et la nature du métal d’électrode en utilisant la méthode de la barrière effective avec les paramètres nécessaires calibrés.• Modéliser l'OG-CNTFET selon les régimes de fonctionnement, lecture, écriture, effacement ou programmation pour application à une mémoire non-volatile en intégrant le mécanisme de piégeage et dépiégeage à l’interface polymère/oxyde. / This PhD thesis presents a computationally efficient physics-based compact model for optically-gated carbon nanotube field effect transistors (OG-CNTFETs), especially in the non-volatile memory application. This model includes memory operations such as “read”, “write”, “erase” or “program”, and “reset” which are modeled using trapping and detrapping mechanisms at the polymer/oxide interface. The relaxation of the memory state is taken into account. Furthermore, the self-consistent modeling of Schottky barriers at contacts between the carbon nanotube channel and metal electrodes is integrated in this model applying the effective Schottky barrier method. The Schottky contact model can be included in CNTFET based devices for a typical biasing range of carbon nanotube transistors. This compact model is validated by the good agreement between simulation results and experimental data (I-V characteristics). In the non-volatile memory application, this model can fully reproduce device behaviors in transient simulations. A prediction study of the key technological parameter, the CNT diameter variety is established to expect its impact on the transistor performance, and more importantly, on the memory operation. In the other hand, this thesis presents a preliminary electric characterization (I-V) of CNTFETs and OG-CNTFETs for the device modeling database. A preliminary optoelectronic characterization method is proposed.

Afin de permettre le développement de modèles manipulables par les concepteurs, il est nécessaire de pouvoir comprendre le fonctionnement des nanotubes, en particulier le transport des électrons et leurs propriétés électroniques. C’est dans ce contexte général que cette thèse s’intègre. Le travail a été mené sur quatre plans : développement de modèles permettant la description des phénomènes physiques importants au niveau des dispositifs, expertise sur le fonctionnement des nano-composants permettant de dégager les ordres de grandeurs pertinents pour les dispositifs, les contraintes, la pertinence de quelques procédés de fabrication (reproductibilité, taux de défauts, collection de caractéristiques mesurées et développement éventuel d'expériences spécifiques, expertise et conception des circuits innovatifs pour l’électronique numérique avec ces nano-composants. / This PhD work presents a computationally efficient physics-based compact model for the Schottky barrier (SB) carbon nanotube field-effect transistor (CNTFET). This compact model includes a new analytical formulation of the channel charge, taking into account the influence of the source and drain SBs. Compact model simulation results (I–V characteristic and channel density of charge) as well as Monte Carlo simulation results, which are provided by a recent work, will be given and compared to each other and also to experimental data to validate the used approximations. Good agreement is observed over a large range of gate and drain biases. Furthermore, a scaling study is presented to examine the impact of technological parameters on the device figure of merit. Then, for the assessment of the SB on circuit performances, traditional logical circuits are designed using the SB-CNTFET compact model, and results are compared with a conventional CNTFET with zero-SB height. Finally, exploiting the particular properties of SB-CNTFETs, a three-valued static memory that is suitable for high density integration is presented.

Metal-semiconductor contacts have been widely studied in the past 60 years. These structures are of importance in the microelectronics industry. As the scaling down of silicon-based complementary metal-oxide-semiconductor (CMOS) devices becomes more and more challenging, new material and device structures to relax this physical limitation in device scaling are now required. Germanium (Ge) has been proposed as a potential alternative to silicon. In this thesis a systematic study of the thermally induced reaction of transition metals with the n-Ge substrate is outlined. Investigations in the change of the electrical properties of the metal germanide structures is studied in a wide range of temperatures. Current-voltage (I-V), capacitance-voltage (C-V), deep level transient spectroscopy (DLTS) and high-resolution Laplace-DLTS (L-DLTS) techniques have been used for the electrical characterization of the fabricated Schottky contacts. Results obtained indicate the variation of the electrical properties of these Schottky contacts can be attributed to combined effects of interfacial reactions and phase transformation during the annealing process. The barrier height distribution in identically prepared Schottky contacts on n-Ge (100) showed that the barrier heights and ideality factors varied from diode to diode even though they were identically fabricated. The properties of the n-Ge Schottky contacts have revealed a strong dependence on temperature. The current transport mechanism has been shown to be predominantly thermionic emission at high temperatures while at low temperatures, the Schottky contacts have exhibited the dominance of the generation-recombination current mechanism. The variation of the Schottky barrier heights at low temperatures have been attributed to barrier inhomogeneities at the metal-semiconductor (MS) interface. Results from defect characterization by DLTS show that the E-centre is the dominant defect introduced in n-Ge by electron beam deposition during contact fabrication and substitutional related defects are induced during the annealing process. The identification of some of the defects was achieved by using defect properties, defect signature, annealing mechanisms and annealing behaviour and comparing these properties to the results from theoretical defect models. Annealing showed that defects in Ge can be removed by low thermal budget of between 250–350°C. Finally, structural characterization of these samples was performed by scanning electron microscopy (SEM) and Rutherford backscattering spectrometry (RBS) techniques. From the SEM images it can be observed that the onset temperature for agglomeration in the 30 nm Ni/n-Ge (100), and Pt/-, Ir/- and Ru/n-Ge (100) systems occur at 500–600°C and 600–700°C, respectively. / Thesis (PhD)--University of Pretoria, 2010. / Physics / unrestricted

No description available.