Abstract The developing trend toward the integreation of many function in application market of semiconductor, makes the original business model of IC design industry to change. From open structure (named ¡§Wintel¡¨ structure) till today, what we can see it shows as transition stage. It will be end in the situation the all devices can interlink to each other. All of us don¡¦t know how long we will overcome this transition stage. But it really challenges the orginal business model of IC design industry. The business model of IC design industry changes along with the changing in product application market. In this study, we do analysis of IC design industry¡¦s business model by four dimensions¡Xmarket strategies, capabilities of technology, the types of organization, financial resources. We will discuss the differents between Taiwan and American IC design industry In market strategy dimension, there are more and more difficults to distinguish between past strategy model including niche and volume strategies. Because the revolution of electronics application market, the better ways for Taiwan IC design industry to develop its market strategy are depending on capability focusing and the capture of market demend. When mentioning about the IC design skill, Taiwan IC design industry can choose several ways to cumulate its design capabilities according to the market strategy it chose. About types of the organization, the combination of fabless and fabless is the trend. Also 1¡¦st tier IDM will be the key roles who dominate the future IC industry. More than all, fabless who belong to system assembly factory or fabless who belong to foundry will be the mainstream in the IC industry and in electronics application market, too. Depending on what kinds of organzation IC design companies chose, it will affect the ability when they rising money. These four factors interaction built the business model of the Taiwan IC design industry.

With continuous and aggressive scaling in semiconductor technology, there is an increasing gap between design expectation and manufactured silicon data. Research on DFM (Design for manufacturability), MFD (Manufacturing for Design) and statistical analysis have been investigated in recent years to bridge design and manufacturing. Fundamentally, layout is the final output from the design side and the input to the manufacturing side. It is also the last chance to dramatically modify the design efficiently and economically. In this dissertation, I present the modeling and optimization work on bridging the gap between design expectation and reality, improving performance and enhancing manufacturing yield. I investigate several stages of semiconductor design development including manufacturing process, device, interconnect, and circuit level. In the manufacturing process stage, a novel inverse lithography technology (ILT) is proposed for sub-wavelength lithography resolution enhancement. New intuitive transformations enable the method to gradually converge to the optimal solution. A highly efficient method for gradient calculation is derived based on partially coherent optical models. Dose variation is considered within the ILO process with the min-max optimization method and the computation overhead on dose process variation could be omitted. The methods are implemented in state-of-the-art industrial 32nm lithography environment. After the work in the lithography process stage provides both mask optimization and post-layout silicon image simulation, my work on the first non-rectangular device modeling card extends the post-layout lithography to post-litho electrical calibration. Based on the lithography simulation results, the non-rectangular gate shapes are extracted and their effect is investigated by the proposed non-rectangular device modeling card and post-litho circuit simulation flow. This work is not only the first non-rectangular device modeling card but also compatible with industry standard device models and the parameter extraction flow. Interconnect plays a more critical role in the nanometer scale IC design especially because of its impact on delay. The scattering effect that occurs in nanoscale wires is modeled and different methods of wire sizing/shaping are discussed. Based on closed-form resistivity model for nanometer scale Cu interconnect, new interconnect delay model and wire sizing/shaping strategies are developed. Based on the advanced modeling of process, device and interconnect, circuit level investigation is focused on statistical timing analysis with a new latch delay model. For the first time, both combinational logic and clock distribution circuits are integrated together through statistical timing of latch outputs. This dissertation studies the new phenomena of nanometer scale IC design and manufacture. Starting from the designed layout, through modeling, optimization and simulation, the work moves ahead to the mask pattern and silicon image, calibrates electrical properties of devices as well as circuits. Through above process, we can better connect layout with silicon data to reach design and manufacturing closure. / text

<p dir="ltr">The adoption of Heterogeneous Integration (HI) technologies in semiconductor packaging to build 2.5D/3D structures has led to increased power densities and material heterogeneity. These structures place a new burden on thermal and mechanical design. Additionally, these structures allow for significantly increased physical design freedom. With more possible layout options as well as tougher thermal constraints, new specialized tools are required to accelerate this type of design.</p><p dir="ltr">To address this problem using traditional finite element analysis Stack3D is presented. Stack3D is a steady-state thermal-mechanical geometry modeling and analysis platform for advanced packaging early design exploration. It is a finite element simulator developed from scratch in Matlab complete with symbolic geometry representation, automatic meshing, chip power map support, and sparse matrix acceleration.</p><p dir="ltr">After the development of Stack3D, methods for further accelerating the simulation process at the cost of solution accuracy were examined. Neural networks were selected as an engine for this task based on their millisecond evaluation time. In order to choose between the training paradigms of Physics Informed and Data Driven neural networks, a series of benchmarks were run to identify Data Driven networks as ideal candidates for steady state heat conduction.</p><p dir="ltr">Last, the first neural network model for fully generalized steady state heat conduction of 3D packages is developed. This is made possible by using the solution to the partial differential equation governing steady state heat conduction and casting the problem into an image-to-image translation framework. After accounting for the third spatial dimension, this allows the use of cutting edge image processing network for the heat conduction problem. After training, the network was able to run tens of thousands of simulations with an average of 0.53\% error and 0.0035 seconds per simulation.</p>