This thesis considers the problem of reconstructing system level behavior of an SoC design from a partially observed signal trace. Solving this problem is a critical activity in post-silicon validation, and currently depends primarily on human creativity and insights. In this thesis, we provide algorithms to automatically infer system level flows from incomplete, ambiguous, and noisy trace data. This thesis also demonstrates the approach on two case studies, a multicore SoC model developed within the within the GEM5 environment, and a cycle accurate register transfer level model of a similar SoC design.

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Post-silicon validation is an important step during the implementation flow of digital integrated circuits and systems. Most of the validation strategies are based on ad-hoc solutions, such as guidelines from best practices, decided on a case-by-case basis for a specific design and/or application domain. Developing systematic approaches for post-silicon validation can mitigate the productivity bottlenecks that have emerged due to both design diversification and shrinking implementation cycles. Ever since integrating on-chip memory blocks became affordable, embedded logic analysis has been used extensively for post-silicon validation. Deciding at design time which signals to be traceable at the post-silicon phase, has been posed as an algorithmic problem a decade ago. Most of the proposed solutions focus on how to restore as much data as possible within a software simulator in order to facilitate the analysis of functional bugs, assuming that there are no electrically-induced design errors, e.g., bit- flips. In this thesis, first it is shown that analyzing the logic inconsistencies from the post-silicon traces can aid with the detection of bit-flips and their root-cause analysis. Furthermore, when a bit-flip is detected, a list of suspect nets can be automatically generated. Since the rate of bit-flip detection as well the size of the list of suspects depends on the debug data that was acquired, it is necessary to select the trace signals consciously. Subsequently, new methods are presented to improve the bit-flip detectability through an algorithmic approach to selecting the on-chip trace signals. Hardware assertion checkers can also be integrated on-chip in order to detect events of interest, as defined by the user. For example, they can detect a violation of a design property that captures a relationship between internal signals that is supposed to hold indefinitely, so long as no bit-flips occur in the physical prototype. Consequently, information collected from hardware assertion checkers can also provide useful debug information during post-silicon validation. Based on this observation, the last contribution from this thesis presents a novel method to concurrently select a set of trace signals and a set of assertions to be integrated on-chip. / Thesis / Doctor of Philosophy (PhD)

Real-time monitoring of electromechanical oscillations is of great significance for power system operators; to this aim, software solutions (algorithms) that use synchrophasor measurements have been developed for this purpose. This thesis investigates different approaches for improving mode estimation process by offering new methods and deepening the understanding of different stages in the mode estimation process. One of the problems tackled in this thesis is the selection of synchrophasor signals used as the input for mode estimation. The proposed selection is performed using a quantitative criterion that is based on the variance of the critical mode estimate. The proposed criterion and associated selection method, offer a systematic and quantitative approach for PMU signal selection. The thesis also analyzes methods for model order selection used in mode estimation. Further, negative effects of forced oscillations and non-white noise load random changes on mode estimation results have been addressed by exploiting the intrinsic power system property that the characteristics of electromechanical modes are predominately determined by the power generation and transmission network. An improved accuracy of the mode estimation process can be obtained by intentionally injecting a probing disturbance. The thesis presents an optimization method that finds the optimal spectrum of the probing signals. In addition, the probing signal with the optimal spectrum is generated considering arbitrary time domain signal constraints that can be imposed by various probing signal generating devices. Finally, the thesis provides a comprehensive description of a practical implementation of a real-time mode estimation tool. This includes description of the hardware, software architecture, graphical user interface, as well as details of the most important components such as the Statnett’s SDK that allows easy access to synchrophasor data streams. / <p>The Doctoral Degrees issued upon completion of the programme are issued by Comillas Pontifical University, Delft University of Technology and KTH Royal Institute of Technology. The invested degrees are official in Spain, the Netherlands and Sweden, respectively.</p><p>QC 20160218</p> / FP7 iTesla

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