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Silicon nanowires have great potential for applications in electronics, photovoltaics and biomedical applications, but as of yet, silicon nanowires are not used in any commercial application. More characterization is needed to better understand and control their surfaces and electronic properties. Here, electron energy loss spectroscopy (EELS) is used to characterize silicon nanowires made by the supercritical-fluid-liquid-solid process. EELS is able to analyze the elemental composition of core and shell structures with high spatial resolution. Additionally, the biocompatibility and antibacterial properties of silicon nanowires are assessed for potential bioapplications. Preliminary investigations suggest that nanowires have an anti-proliferative effect on E. coli and discourage adhesion of mammalian cells. Future investigations may prove that silicon nanowires are a promising material for biomedical implant coatings to prevent biofouling. / text

published_or_final_version / abstract / toc / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

published_or_final_version / abstract / toc / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

published_or_final_version / Physics / Master / Master of Philosophy

published_or_final_version / Physics / Master / Master of Philosophy

In this investigation, controlled thermal annealing and oxidation treatments were carried out on wafers obtained from seed-end and tang-end regions of (100)-oriented, 75 mm-diameter, Czochralski-grown, "typical" silicon single crystals. The radial variation of resistivity was characterized with four-point probe and spreading resistance probe measurements. The defects were studied by preferential etching and optical microscopy, using Wright etch for characterizing the individual etch figures, whereas the overall distribution of defects was obtained by using a modified form of Sirtl etch. The preferential etching was carried out in a Teflon barrel under controlled conditions. Transmission electron microscopy (TEM) was carried out on selected samples to study the defect structure in the as-grown crystal as well as after specific thermal treatments. In the p-type as well as n-type crystals studied in this work, the relative radial gradient as well as the magnitude of resistivity are greater at the seed-end than at the tang-end. An annealing treatment at 650°C for 100 min on seed-end wafers stabilized the resisitivity by destroying oxygen-donor complexes. Such an annealing treatment on tang-end wafers has a minor effect on the resistivity of the sample, which was uniform initially. The "swirl" patterns, as revealed by preferential etching, showed that they are more pronounced in seed-end wafers and are almost absent in tang-end wafers. A pre-annealing treatment at 650°C in argon for 100 min followed by a high-temperature (≥800°C) treatment precipitates the swirl pattern much more intensely, in comparison to just the high temperature treatment without any preanneal at 650°C. For comparable oxide thicknesses (0.5 μm) for thermal oxidation in steam at three different temperatures (900°C, 1050°C, 1200°C), it was found that the swirl pattern was most severe at 900°C and the dissolution of the defect structure progressively increased with increasing temperature. It was found in this investigation that bulk-type stacking faults are generated after argon annealing at 1050°C. This is in contrast to the generally prevailing confusion that thermal oxidation is essential for generation of stacking faults in silicon. It must be distinguished here that the formation of surface-type stacking faults requires thermal oxidation, whereas bulk-type stacking faults nucleate at individual swirl defects due to precipitation of dissolved oxygen. TEM work done in this investigation showed that as-grown CZ silicon defect structure consists of an assortment of precipitates, small dislocation lines, and a helical type of long (∼24 μm) dislocation line, and another long linear defect with periodically spaced nodes. The annealing treatment at 650°C as well as thermal oxidation at 900°C produce a spectrum of precipitates and small dislocations.

No description available.

There has been an exponential increase in the performance of silicon based semiconductor devices in the past few decades. This improvement has mainly been due to dimensional scaling of the MOSFET. However, physical constraints limit the continued growth in device performance. To overcome this problem, novel channel materials are being developed to enhance carrier mobility and hence increase device performance. This work explores a novel semiconducting alloy - Silicon-tin (SiSn) as a channel material for CMOS applications. For the first time ever, MOS devices using SiSn as channel material have been demonstrated. A low cost, scalable and manufacturable process for obtaining SiSn by diffusion of Sn into silicon has also been explored. The channel material thus obtained is electrically characterized by fabricating MOSCAPs and Mesa-shaped MOSFETs. The SiSn devices have been compared to similar devices fabricated using silicon as channel material.

No description available.