Simultaneous recordings of single and multi-unit neural signals from multiple cortical areas in the brain are a vital tool for gaining more understanding of the operating mechanism of the brain as well as for developing Brain Machine Interfaces. Monitoring the activity levels of hundreds or even thousands of neurons can lead to reliable decoding of brain signals for controlling prosthesis of multiple degrees of freedom and different functionalities. With the advancement of high density microelectrode arrays, the craving of neuroscience research to record the activity of thousands of neurons is achievable. Recently CMOS-based Micro-electrode Arrays MEAs featuring high spatial and temporal resolution have been reported. The augmentation in the number of recording sites carries different challenges to the neural signal processing system. The primary challenge is the massive increase in the incoming data that needs to be transmitted and processed in real time. Data reduction based on the sparse nature of the neural signals with respect to time becomes essential. The dissertation presents the design of a neural spike-based data reduction platform that can handle a few thousands of channels on Field Programmable Gate Arrays (FPGAs), making use of their massive parallel processing capabilities and reconfigurability. For Standalone implementation the spike detector core uses Finite State Machines (FSMs) to control the interface with the data acquisition as well as sending the spike waveforms to a common output FIFO. The designed neural signal processing platform integrates the application of high-speed serial Multi-Gigabit transceivers on FPGAs to allow massive data transmission in real time. It also provides a design for autonomous threshold setting for each channel. / Electrical and Computer Engineering

A terrestrial robotic electrophysiology platform has been developed that can hold a moth (<italic>Manduca sexta</italic>), record signals from its brain or muscles, and use these signals to control the rotation of the robot. All signal processing (electrophysiology, spike detection, and robotic control) was performed onboard the robot with custom designed electronic circuits. Wireless telemetry allowed remote communication with the robot. In this study, we interfaced directionally-sensitive visual neurons and pleurodorsal steering muscles of the mesothorax with the robot and used the spike rate of these signals to control its rotation, thereby emulating the classical optomotor response known from studies of the fly visual system. The interfacing of insect and machine can contribute to our understanding of the neurobiological processes underlying behavior and also suggest promising advancements in biosensors and human brain-machine interfaces.

abstract: Interictal spikes, together with seizures, have been recognized as the two hallmarks of epilepsy, a brain disorder that 1% of the world's population suffers from. Even though the presence of spikes in brain's electromagnetic activity has diagnostic value, their dynamics are still elusive. It was an objective of this dissertation to formulate a mathematical framework within which the dynamics of interictal spikes could be thoroughly investigated. A new epileptic spike detection algorithm was developed by employing data adaptive morphological filters. The performance of the spike detection algorithm was favorably compared with others in the literature. A novel spike spatial synchronization measure was developed and tested on coupled spiking neuron models. Application of this measure to individual epileptic spikes in EEG from patients with temporal lobe epilepsy revealed long-term trends of increase in synchronization between pairs of brain sites before seizures and desynchronization after seizures, in the same patient as well as across patients, thus supporting the hypothesis that seizures may occur to break (reset) the abnormal spike synchronization in the brain network. Furthermore, based on these results, a separate spatial analysis of spike rates was conducted that shed light onto conflicting results in the literature about variability of spike rate before and after seizure. The ability to automatically classify seizures into clinical and subclinical was a result of the above findings. A novel method for epileptogenic focus localization from interictal periods based on spike occurrences was also devised, combining concepts from graph theory, like eigenvector centrality, and the developed spike synchronization measure, and tested very favorably against the utilized gold rule in clinical practice for focus localization from seizures onset. Finally, in another application of resetting of brain dynamics at seizures, it was shown that it is possible to differentiate with a high accuracy between patients with epileptic seizures (ES) and patients with psychogenic nonepileptic seizures (PNES). The above studies of spike dynamics have elucidated many unknown aspects of ictogenesis and it is expected to significantly contribute to further understanding of the basic mechanisms that lead to seizures, the diagnosis and treatment of epilepsy. / Dissertation/Thesis / Ph.D. Electrical Engineering 2012

Learning is central to infusing intelligence to any biologically inspired system. This study introduces a novel Cross-Correlated Delay Shift (CCDS) learning method for spiking neurons with the ability to learn and reproduce arbitrary spike patterns in a supervised fashion with applicability tospatiotemporalinformation encoded at the precise timing of spikes. By integrating the cross-correlated term,axonaland synapse delays, the CCDS rule is proven to be both biologically plausible and computationally efficient. The proposed learning algorithm is evaluated in terms of reliability, adaptive learning performance, generality to different neuron models, learning in the presence of noise, effects of its learning parameters and classification performance. The results indicate that the proposed CCDS learning rule greatly improves classification accuracy when compared to the standards reached with the Spike Pattern Association Neuron (SPAN) learning rule and the Tempotron learning rule. Network structureis the crucial partforany application domain of Artificial Spiking Neural Network (ASNN). Thus, temporal learning rules in multilayer spiking neural networks are investigated. As extensions of single-layer learning rules, the multilayer CCDS (MutCCDS) is also developed. Correlated neurons are connected through fine-tuned weights and delays. In contrast to the multilayer Remote Supervised Method (MutReSuMe) and multilayertempotronrule (MutTmptr), the newly developed MutCCDS shows better generalization ability and faster convergence. The proposed multilayer rules provide an efficient and biologically plausible mechanism, describing how delays and synapses in the multilayer networks are adjusted to facilitate learning. Interictalspikes (IS) aremorphologicallydefined brief events observed in electroencephalography (EEG) records from patients with epilepsy. The detection of IS remains an essential task for 3D source localization as well as in developing algorithms for seizure prediction and guided therapy. In this work, we present a new IS detection method using the Wavelet Encoding Device (WED) method together with CCDS learning rule and a specially designed Spiking Neural Network (SNN) structure. The results confirm the ability of such SNN to achieve good performance for automatically detecting such events from multichannel EEG records.

No description available.

No description available.

In this work, the problem of detecting neuronal spikes or action potentials (AP) in noisy recordings from a Microelectrode Array (MEA) is investigated. In particular, the spike detection algorithms should be less complex and with low computational complexity so as to be amenable for real time applications. The use of the MEA is that it allows collection of extracellular signals from either a single unit or multiple (45) units within a small area. The noisy MEA recordings then undergo basic filtering, digitization and are presented to a computer for further processing. The challenge lies in using this data for detection of spikes from neuronal firings and extracting spatiotemporal patterns from the spike train which may allow control of a robotic limb or other neuroprosthetic device directly from the brain. The aim is to understand the spiking action of the neurons, and use this knowledge to devise efficient algorithms for Brain Machine Interfaces (BMIs). An effective BMI will require a realtime, computationally efficient implementation which can be carried out on a DSP board or FPGA system. The aim is to devise algorithms which can detect spikes and underlying spatio-temporal correlations having computational and time complexities to make a real time implementation feasible on a specialized DSP chip or an FPGA device. The time-frequency localization, multiresolution representation and analysis properties of wavelets make them suitable for analysing sharp transients and spikes in signals and distinguish them from noise resembling a transient or the spike. Three algorithms for the detection of spikes in low SNR MEA neuronal recordings are proposed: 1. A wavelet denoising method based on the Discrete Wavelet Transform (DWT) to suppress the noise power in the MEA signal or improve the SNR followed by standard thresholding techniques to detect the spikes from the denoised signal. 2. Directly thresholding the coefficients of the Stationary (Undecimated) Wavelet Transform (SWT) to detect the spikes. 3. Thresholding the output of a Teager Energy Operator (TEO) applied to the signal on the discrete wavelet decomposed signal resulting in a multiresolution TEO framework. The performance of the proposed three wavelet based algorithms in terms of the accuracy of spike detection, percentage of false positives and the computational complexity for different types of wavelet families in the presence of colored AR(5) (autoregressive model with order 5) and additive white Gaussian noise (AWGN) is evaluated. The performance is further evaluated for the wavelet family chosen under different levels of SNR in the presence of the colored AR(5) and AWGN noise. Chapter 1 gives an introduction to the concept behind Brain Machine Interfaces (BMIs), an overview of their history, the current state-of-the-art and the trends for the future. It also describes the working of the Microelectrode Arrays (MEAs). The generation of a spike in a neuron, the proposed mechanism behind it and its modeling as an electrical circuit based on the Hodgkin-Huxley model is described. An overview of some of the algorithms that have been suggested for spike detection purposes whether in MEA recordings or Electroencephalographic (EEG) signals is given. Chapter 2 describes in brief the underlying ideas that lead us to the Wavelet Transform paradigm. An introduction to the Fourier Transform, the Short Time Fourier Transform (STFT) and the Time-Frequency Uncertainty Principle is provided. This is followed by a brief description of the Continuous Wavelet Transform and the Multiresolution Analysis (MRA) property of wavelets. The Discrete Wavelet Transform (DWT) and its filter bank implementation are described next. It is proposed to apply the wavelet denoising algorithm pioneered by Donoho, to first denoise the MEA recordings followed by standard thresholding technique for spike detection. Chapter 3 deals with the use of the Stationary or Undecimated Wavelet Transform (SWT) for spike detection. It brings out the differences between the DWT and the SWT. A brief discussion of the analysis of non-stationary time series using the SWT is presented. An algorithm for spike detection based on directly thresholding the SWT coefficients without any need for reconstructing the denoised signal followed by thresholding technique as in the first method is presented. In chapter 4 a spike detection method based on multiresolution Teager Energy Operator is discussed. The Teager Energy Operator (TEO) picks up localized spikes in signal energy and thus is directly used for spike detection in many applications including R wave detection in ECG and various (alpha, beta) rhythms in EEG. Some basic properties of the TEO are discussed followed by the need for a multiresolution approach to TEO and the methods existing in literature. The wavelet decomposition and the subsampled signal involved at each level naturally lends it to a multiresolution TEO framework at the same time significantly reducing the computational complexity due the subsampled signal at each level. A wavelet-TEO algorithm for spike detection with similar accuracies as the previous two algorithms is proposed. The method proposed here differs significantly from that in literature since wavelets are used instead of time domain processing. Chapter 5 describes the method of evaluation of the three algorithms proposed in the previous chapters. The spike templates are obtained from MEA recordings, resampled and normalized for use in spike trains simulated as Poisson processes. The noise is modeled as colored autoregressive (AR) of order 5, i.e AR(5), as well as Additive White Gaussian Noise (AWGN). The noise in most human and animal MEA recordings conforms to the autoregressive model with orders of around 5. The AWGN Noise model is used in most spike detection methods in the literature. The performance of the proposed three wavelet based algorithms is measured in terms of the accuracy of spike detection, percentage of false positives and the computational complexity for different types of wavelet families. The optimal wavelet for this purpose is then chosen from the wavelet family which gives the best results. Also, optimal levels of decomposition and threshold factors are chosen while maintaining a balance between accuracy and false positives. The algorithms are then tested for performance under different levels of SNR with the noise modeled as AR(5) or AWGN. The proposed wavelet based algorithms exhibit a detection accuracy of approximately 90% at a low SNR of 2.35 dB with the false positives below 5%. This constitutes a significant improvement over the results in existing literature which claim an accuracy of 80% with false positives of nearly 10%. As the SNR increases, the detection accuracy increases to close to 100% and the false alarm rate falls to 0. Chapter 6 summarizes the work. A comparison is made between the three proposed algorithms in terms of detection accuracy and false positives. Directions in which future work may be carried out are suggested.

O registro de sinais neurais através de matrizes de microeletrodos implantáveis no meio extracelular do córtex cerebral tem-se tornado um paradigma experimental para a neurociência. Por outro lado, a pesquisa recente sobre neuropróteses motoras tem mostrado que é possível decodificar comandos motores a partir dos sinais registrados no meio extracelular do córtex cerebral. Em ambos os contextos, neurociência experimental e desenvolvimento de neuropróteses motoras, um dos aspectos encontrados no estado da arte ´e a utilização de circuitos integrados (chips) implantados no cérebro. Nesses chips, os sinais neurais medidos com os microeletrodos são amplificados, filtrados, processados e transmitidos a um computador externo mediante fios que atravessam o crânio. Existe o interesse em desenvolver chips implantáveis que transmitam os sinais ao computador externo sem a necessidade de fios que atravessem o crânio. Na pesquisa do estado da arte tem-se encontrado a utilização de tais chips implantáveis sem fio em ratos e macacos, porém até a data da elaboração deste texto não foram encontrados relatos da aplicação em humanos. Um dos aspectos que deve se levar em consideração no desenvolvimento de interfaces neurais implantáveis sem fio é a largura de banda do canal de comunicação. Quanto maior a quantidade de dados a serem transmitidos, maior a largura de banda necessária e maior o aquecimento do chip devido à dissipação de potência. Esta tese aborda sistemas de processamento de sinais neurais extracelulares que tem como objetivo reduzir a quantidade de dados a serem transmitidos e assim viabilizar a transmissão sem fio. Para poder ser integrados dentro do chip implantável, esses sistemas de processamento devem estar otimizados em termos de área e consumo de potência. Dois processamentos encontrados na pesquisa de interfaces neurais implantáveis são a detecção de impulsos elétricos e a separação de impulsos elétricos (Spike Sorting). Nesta tese apresentam-se soluções para esses tipos de processamentos visando a implementação mediante tecnologia CMOS (Complementary Metal Oxide Semiconductor). Para o caso da detecção de impulsos elétricos (spikes), nesta tese apresenta-se uma alternativa de implementação em hardware de um operador matemático conhecido como operador não linear de energia (NEO do inglês Nonlinear Energy Operator) ou operador Teager. Através da aplicação desse operador a um sinal neural evidencia-se a presença de spikes e atenua-se o ruído. Uma das características inovadoras da implementação apresentada nesta tese é a utilização de um circuito elevador ao quadrado que consiste de apenas três transistores, como bloco funcional básico para a realização da operação NEO. O circuito NEO desenvolvido consome 300 pJ no processamento de um spike e foi caracterizado por simulação até em 30 kHz, frequência que é compatível com as taxas de amostragem encontradas na literatura. O outro processamento abordado nesta tese, conhecido como separação de impulsos elétricos ou Spike Sorting, consiste no agrupamento dos impulsos elétricos registrados por um eletrodo em categorias, de maneira que em uma categoria estejam os impulsos gerados por um mesmo neurônio. Em outras palavras, o objetivo é reconhecer quais dos impulsos elétricos medidos pelo eletrodo pertencem a um mesmo neurônio, sendo possível que vários neurônios influenciem na medida realizada por um único eletrodo. Uma solução para a separação de impulsos, apropriada no contexto de sistemas implantáveis, é o template matching. Essa técnica baseia-se na geração de modelos (templates) durante uma fase inicial ao final da qual o número de templates gerados corresponde ao número de neurônios identificados pelo eletrodo. Numa fase seguinte, o sistema associa cada impulso elétrico detectado a um dos modelos inicialmente gerados. Nesta tese propõe-se um sistema de classificação que executa essa segunda fase do processo de spike sorting. Nesta tese apresenta-se o projeto de um sistema de classificação de spikes baseado na t écnica template matching, implementado com tecnologia CMOS. A implementação proposta nesta tese baseia-se na representação de amostras analógicas mediante o tempo. Esse tipo de representação de sinais analógicos mediante atrasos de pulsos digitais está sendo muito utilizado como alternativa à representação no domínio da tensão, da corrente ou da carga elétrica. A vantagem desse tipo de representação é que não se vê severamente afetada pela redução da tensão de alimentação dos circuitos integrados fabricados em tecnologias submicrométricas. A taxa de acerto na classificação do sistema desenvolvido é maior que 99% inclusive considerando um offset de até 20mV no comparador de saída. Os circuitos apresentados neste trabalho foram projetados considerando dispositivos da tecnologia TSMC de 90nm. / Neural signals recording through implantable microelectrode arrays in cortex extracellular medium has become an experimental paradigm for neuroscience. Moreover, recent research about motor neuroprostheses has shown that it is possible to decode motor commands from the signals recorded in the cerebral cortex extracellular medium. In both situations, experimental neuroscience and motor neuroprostheses development, one of the issues encountered in the state-of-the-art is the use of integrated circuits (chips) implanted in the brain. In these chips, neural signals measured with microelectrodes are amplified, filtered, processed, and transmitted to an external computer through wires that run through the skull. There is interest in developing implantable chips that transmit signals to the external computer without the need for wires passing through the skull. In the survey of the state-of-the-art it has found the use of such implantable wireless chips in rats and monkeys, but until the date of this writing we have not found reports of application in humans. One of the aspects that must be taken into account in the development of wireless implantable neural interfaces is the bandwidth of the communication channel. The greater the amount of data to be transmitted, the greater the bandwidth required and higher chip heating due to power dissipation. This thesis deals with extracellular neural signals processing systems that aim to reduce the amount of data to be transmitted and in this way to enable wireless transmission. In order to integrate them into an implantable chip, those processing systems must be optimized in terms of area and power consumption. Two processes found in the research of implantable neural interfaces are spike detection and spike sorting. In this thesis solutions for these types of processing are presented considering their implementation by CMOS (Complementary Metal Oxide Semiconductor). For the case of spike detection in this thesis it is presented an alternative for the hardware implementation of a mathematical operator known as NEO (Nonlinear Energy Operator). Through the application of this operator to a neural signal the presence of spikes becomes evident and the noise is attenuated. One of the innovative characteristics of the implementation presented in this thesis is the use of a squarer circuit which consists of only three transistors, as a basic function block for performing operation of NEO. NEO circuit consumes 300 pJ in processing a spike, and was characterized by simulation up to 30 kHz, frequency which is compatible with sampling rates found in the literature. The other processing discussed in this thesis, known as Spike Sorting, is the grouping of electrical impulses recorded by an electrode into categories so that the spikes belonging to the same category were generated by a single neuron. In other words, the goal is to recognize which of the spikes measured by the electrode belong to the same neuron, given that it is possible that several neurons influence the measure performed by a single electrode. A solution for the Spike Sorting suitable in the context of implantable systems, is the template matching. This technique is based on generating templates during an initial phase at the end of which the number of generated templates corresponds to the number of neurons identified by the electrode. In the next phase, the system associates each detected spike to one of the templates generated initially. In this thesis it is proposed a classification systems which performs that second phase of the spike sorting process. This thesis presents the design of a spike classification system based on template matching technique, implemented in CMOS technology. The processing proposed in this work is based on the time-based representation of the analog samples. This kind of representation of analog signals by delays of digital pulses is being widely used as an alternative to the classical representation of samples by voltage, current or electric charge. The advantage of this time-mode representation is that it is not severely affected by reduced supply voltage of integrated circuits manufactured in sub-micrometer technologies. The classification hit rate of the developed system is greater than 99% even when an offset of 20 mV is assumed for the output comparator. All the circuits presented in this work were designed using devices from TSMC 90nm technology.

O registro de sinais neurais através de matrizes de microeletrodos implantáveis no meio extracelular do córtex cerebral tem-se tornado um paradigma experimental para a neurociência. Por outro lado, a pesquisa recente sobre neuropróteses motoras tem mostrado que é possível decodificar comandos motores a partir dos sinais registrados no meio extracelular do córtex cerebral. Em ambos os contextos, neurociência experimental e desenvolvimento de neuropróteses motoras, um dos aspectos encontrados no estado da arte ´e a utilização de circuitos integrados (chips) implantados no cérebro. Nesses chips, os sinais neurais medidos com os microeletrodos são amplificados, filtrados, processados e transmitidos a um computador externo mediante fios que atravessam o crânio. Existe o interesse em desenvolver chips implantáveis que transmitam os sinais ao computador externo sem a necessidade de fios que atravessem o crânio. Na pesquisa do estado da arte tem-se encontrado a utilização de tais chips implantáveis sem fio em ratos e macacos, porém até a data da elaboração deste texto não foram encontrados relatos da aplicação em humanos. Um dos aspectos que deve se levar em consideração no desenvolvimento de interfaces neurais implantáveis sem fio é a largura de banda do canal de comunicação. Quanto maior a quantidade de dados a serem transmitidos, maior a largura de banda necessária e maior o aquecimento do chip devido à dissipação de potência. Esta tese aborda sistemas de processamento de sinais neurais extracelulares que tem como objetivo reduzir a quantidade de dados a serem transmitidos e assim viabilizar a transmissão sem fio. Para poder ser integrados dentro do chip implantável, esses sistemas de processamento devem estar otimizados em termos de área e consumo de potência. Dois processamentos encontrados na pesquisa de interfaces neurais implantáveis são a detecção de impulsos elétricos e a separação de impulsos elétricos (Spike Sorting). Nesta tese apresentam-se soluções para esses tipos de processamentos visando a implementação mediante tecnologia CMOS (Complementary Metal Oxide Semiconductor). Para o caso da detecção de impulsos elétricos (spikes), nesta tese apresenta-se uma alternativa de implementação em hardware de um operador matemático conhecido como operador não linear de energia (NEO do inglês Nonlinear Energy Operator) ou operador Teager. Através da aplicação desse operador a um sinal neural evidencia-se a presença de spikes e atenua-se o ruído. Uma das características inovadoras da implementação apresentada nesta tese é a utilização de um circuito elevador ao quadrado que consiste de apenas três transistores, como bloco funcional básico para a realização da operação NEO. O circuito NEO desenvolvido consome 300 pJ no processamento de um spike e foi caracterizado por simulação até em 30 kHz, frequência que é compatível com as taxas de amostragem encontradas na literatura. O outro processamento abordado nesta tese, conhecido como separação de impulsos elétricos ou Spike Sorting, consiste no agrupamento dos impulsos elétricos registrados por um eletrodo em categorias, de maneira que em uma categoria estejam os impulsos gerados por um mesmo neurônio. Em outras palavras, o objetivo é reconhecer quais dos impulsos elétricos medidos pelo eletrodo pertencem a um mesmo neurônio, sendo possível que vários neurônios influenciem na medida realizada por um único eletrodo. Uma solução para a separação de impulsos, apropriada no contexto de sistemas implantáveis, é o template matching. Essa técnica baseia-se na geração de modelos (templates) durante uma fase inicial ao final da qual o número de templates gerados corresponde ao número de neurônios identificados pelo eletrodo. Numa fase seguinte, o sistema associa cada impulso elétrico detectado a um dos modelos inicialmente gerados. Nesta tese propõe-se um sistema de classificação que executa essa segunda fase do processo de spike sorting. Nesta tese apresenta-se o projeto de um sistema de classificação de spikes baseado na t écnica template matching, implementado com tecnologia CMOS. A implementação proposta nesta tese baseia-se na representação de amostras analógicas mediante o tempo. Esse tipo de representação de sinais analógicos mediante atrasos de pulsos digitais está sendo muito utilizado como alternativa à representação no domínio da tensão, da corrente ou da carga elétrica. A vantagem desse tipo de representação é que não se vê severamente afetada pela redução da tensão de alimentação dos circuitos integrados fabricados em tecnologias submicrométricas. A taxa de acerto na classificação do sistema desenvolvido é maior que 99% inclusive considerando um offset de até 20mV no comparador de saída. Os circuitos apresentados neste trabalho foram projetados considerando dispositivos da tecnologia TSMC de 90nm. / Neural signals recording through implantable microelectrode arrays in cortex extracellular medium has become an experimental paradigm for neuroscience. Moreover, recent research about motor neuroprostheses has shown that it is possible to decode motor commands from the signals recorded in the cerebral cortex extracellular medium. In both situations, experimental neuroscience and motor neuroprostheses development, one of the issues encountered in the state-of-the-art is the use of integrated circuits (chips) implanted in the brain. In these chips, neural signals measured with microelectrodes are amplified, filtered, processed, and transmitted to an external computer through wires that run through the skull. There is interest in developing implantable chips that transmit signals to the external computer without the need for wires passing through the skull. In the survey of the state-of-the-art it has found the use of such implantable wireless chips in rats and monkeys, but until the date of this writing we have not found reports of application in humans. One of the aspects that must be taken into account in the development of wireless implantable neural interfaces is the bandwidth of the communication channel. The greater the amount of data to be transmitted, the greater the bandwidth required and higher chip heating due to power dissipation. This thesis deals with extracellular neural signals processing systems that aim to reduce the amount of data to be transmitted and in this way to enable wireless transmission. In order to integrate them into an implantable chip, those processing systems must be optimized in terms of area and power consumption. Two processes found in the research of implantable neural interfaces are spike detection and spike sorting. In this thesis solutions for these types of processing are presented considering their implementation by CMOS (Complementary Metal Oxide Semiconductor). For the case of spike detection in this thesis it is presented an alternative for the hardware implementation of a mathematical operator known as NEO (Nonlinear Energy Operator). Through the application of this operator to a neural signal the presence of spikes becomes evident and the noise is attenuated. One of the innovative characteristics of the implementation presented in this thesis is the use of a squarer circuit which consists of only three transistors, as a basic function block for performing operation of NEO. NEO circuit consumes 300 pJ in processing a spike, and was characterized by simulation up to 30 kHz, frequency which is compatible with sampling rates found in the literature. The other processing discussed in this thesis, known as Spike Sorting, is the grouping of electrical impulses recorded by an electrode into categories so that the spikes belonging to the same category were generated by a single neuron. In other words, the goal is to recognize which of the spikes measured by the electrode belong to the same neuron, given that it is possible that several neurons influence the measure performed by a single electrode. A solution for the Spike Sorting suitable in the context of implantable systems, is the template matching. This technique is based on generating templates during an initial phase at the end of which the number of generated templates corresponds to the number of neurons identified by the electrode. In the next phase, the system associates each detected spike to one of the templates generated initially. In this thesis it is proposed a classification systems which performs that second phase of the spike sorting process. This thesis presents the design of a spike classification system based on template matching technique, implemented in CMOS technology. The processing proposed in this work is based on the time-based representation of the analog samples. This kind of representation of analog signals by delays of digital pulses is being widely used as an alternative to the classical representation of samples by voltage, current or electric charge. The advantage of this time-mode representation is that it is not severely affected by reduced supply voltage of integrated circuits manufactured in sub-micrometer technologies. The classification hit rate of the developed system is greater than 99% even when an offset of 20 mV is assumed for the output comparator. All the circuits presented in this work were designed using devices from TSMC 90nm technology.

Analyzing the brain's behavior in terms of its neuronal activity is the fundamental purpose of Brain-Machine Interfaces (BMIs). Neuronal activity is often assumed to be encoded in the rate of neuronal action potential spikes. Successful performance of a BMI system is tied to the efficiency of its individual processing elements such as spike detection, sorting and decoding. To achieve reliable operation, BMIs are equipped with hundreds of electrodes at the neural interface. While a single electrode/tetrode communicates with up to four neurons at a given instant of time, a typical interface communicates with an ensemble of hundreds or even thousands of neurons. However, translation of these signals (data) into usable information for real-time BMIs is bottlenecked due to the lack of efficient real-time algorithms and real-time hardware that can handle massively parallel channels of neural data. The research presented here addresses this issue by developing real-time neural processing algorithms that can be implemented in reconfigurable hardware and thus, can be scaled to handle thousands of channels in parallel. The developed reconfigurable system serves as an evaluation platform for investigating the fundamental design tradeoffs in allocating finite hardware resources for a reliable BMI. In this work, the generic architectural layout needed to process neural signals in a massive scale is discussed. A System-on-Chip design with embedded system architecture is presented for FPGA hardware realization that features (a) scalability (b) reconfigurability, and (c) real-time operability. A prototype design incorporating a dual processor system and essential neural signal processing routines such as real-time spike detection and sorting is presented. Two kinds of spike detectors, a simple threshold-based and non-linear energy operator-based, were implemented. To achieve real-time spike sorting, a fuzzy logic-based spike sorter was developed and synthesized in the hardware. Furthermore, a real-time kernel to monitor the high-level interactions of the system was implemented. The entire system was realized in a platform FPGA (Xilinx Virtex-5 LX110T). The system was tested using extracellular neural recordings from three different animals, a owl monkey, a macaque and a rat. Operational performance of the system is demonstrated for a 300 channel neural interface. Scaling the system to 900 channels is trivial. / Electrical and Computer Engineering