Submitted by PPG Engenharia El?trica (engenharia.pg.eletrica@pucrs.br) on 2017-10-03T14:30:54Z No. of bitstreams: 1 dissertacao_Marco_tulio.pdf: 5515221 bytes, checksum: 0531f41d66bffa4a34ad4958a41c2d61 (MD5) / Approved for entry into archive by Caroline Xavier (caroline.xavier@pucrs.br) on 2017-10-04T13:10:44Z (GMT) No. of bitstreams: 1 dissertacao_Marco_tulio.pdf: 5515221 bytes, checksum: 0531f41d66bffa4a34ad4958a41c2d61 (MD5) / Made available in DSpace on 2017-10-04T13:17:57Z (GMT). No. of bitstreams: 1 dissertacao_Marco_tulio.pdf: 5515221 bytes, checksum: 0531f41d66bffa4a34ad4958a41c2d61 (MD5) Previous issue date: 2016-05-27 / With advances in technology and miniaturization of CMOS, reliability during the life cycle of Integrated Circuit (IC) becomes a complex concern for critical applications. Miniaturization brings many benefits as high performance, power consumption and increase number of functions inside of IC. However, alongside with these, the benefits for increase of interconnections and density of such SoCs create new challenges for the industry. Moreover, a chip needs to store more and more information, resulting in the fact that SRAM occupy the greatest part of SoCs. Consequently, technology advances need to increase the transistor?s density, turnning them a critical concern for testing and reliability to be analysed after manufacturing, since it creates new types of defects. Defects during manufacture process, as well as Negative Bias Temperature Instability (NBTI), Hot Carrier Injection (HCI) and Electromagnetic Interference (EMI) phenomena represent important challenges that must be addressed at an early stages and over the IC?s life-time. In this context, understanding these phenomena and how they affect technologies below 65nm is essential to ensure reliability required for critical applications. In addition, another source of defects is related to process variations during manufacture. Such defects, like resistive-open and resistive-bridge, appear as the most incident. These defects occur due to small geometric changes in the cell, resulting in static and dynamic failures. Depending on the size of defect they can be considered as weak-defects, which do not result in faulty behaviour at logic level and are not sensitized in conventional manufacturing tests. Note that dynamic faults are considered most responsible for testescapes during manufacturing test. Another important phenomena that affects the reliability of ICs over time is NBTI, causing the aging of SRAMs. In this context, this work proposes to analyze the impact of NBTI in SRAM cells with weak resistive-open and resistive-bridge defects that can escape manufacturing tests due to their dynamic behaviour but, with aging, may become dynamic faults over time. / Com o avan?o tecnol?gico e a miniaturiza??o da tecnologia CMOS, garantir a confiabilidade durante a vida ?til de Circuitos Integrados (CI) tem se tornado um ponto extremamente complexo e importante para aplica??es consideradas cr?ticas. Muitos s?o os benef?cios que esses avan?os trouxeram, como aumento do desempenho, frequ?ncia de opera??o, CIs com capacidade para novas e mais complexas funcionalidades entre outros. Entretanto, com o aumento do n?mero de interconex?es e densidade dos System-on-chip (SoC) novos desafios surgiram e necessitam ser solucionados para que estes avan?os possam continuar. Avan?os tecnol?gicos possibilitaram a fabrica??o de componentes com uma maior densidade de transistores em uma pequena ?rea de sil?cio, tornando-se um ponto cr?tico para o teste e an?lise da confiabilidade ap?s sua fabrica??o, uma vez que esse processo de fabrica??o gera novos tipos de defeitos. Neste sentido, defeitos do tipo resistive-open e resistive-bridge aparecem como os mais prov?veis. Esses defeitos ocorrem devido a pequenas mudan?as geom?tricas das c?lulas e podem causar falhas est?ticas, bem como falhas din?micas. Da mesma forma, fen?menos como Negative Bias Temperature Instability (NBTI), Positive Bias Temperature Instability (PBTI), Hot Carrier Injection (HCI) e Electromagnetic Interference (EMI) representam importantes desafios que obrigatoriamente devem ser tratados desde a fase inicial de projeto de CIs, bem como durante toda a sua vida ?til. Assim, compreender esses fen?menos e como os mesmos afetam tecnologias abaixo de 65nm ? considerado fundamental a fim de garantir a confiabilidade exigida para aplica??es consideradas cr?ticas. Neste contexto, esse trabalho visa avaliar o impacto de defeitos resistivos do tipo resistiveopen e resistive-bridge nas c?lulas de mem?ria do tipo 6T, que passaram nos testes de manufatura, mas que, ao longo dos anos manifestaram falha devido a presen?a do fen?meno de NBTI. Esses defeitos foram modelados atrav?s da inser??o de resist?ncias em determinados pontos da c?lula de mem?ria. Foi observado que defeitos do tipo resistive-open e resistive-bridge quando presentes entre os inversores de uma c?lula de mem?ria e n?o detectados durante os testes de manufatura, resultaram em falha nas opera??es de leitura da c?lula ao longo dos anos quando na presen?a de NBTI. Essa falha apresenta-se inicialmente com um comportamento din?mico e, de acordo com o envelhecimento da c?lula, passa a comporta-se como est?tica. Essa situa??o compromete a confiabilidade da c?lula, uma vez que o tempo de vida estimado da c?lula ser? inferior ao projetado.

Video decoders play a very important role in the TV receivers. This is especially true for NTSC-based TVs. The design and implementation of the video decoder with two-line delay comb filter are presented. Moreover, the works includes the low-power SRAM (static random access memory) in the comb filter for storing scanning line data and the low-power small-area I/O cells for transmitting digital data. A digital phase lock loop (PLL) in the proposed video decoder uses a ROM-less 4£c-based direct digital frequency synthesizer (DDFS)-based digital control oscillator to resolve the false locking problem. Two 20-tap transposed FIRs (finite-duration impulse response filter) are used to implement the low pass filters (LPF) in the chrominance demodulator. Besides, the unnecessary decimals of the coefficients of the LPF are truncated to reduce hardware cost. The proposed SRAM takes advantage of a negative word-line voltage controlling the access transistors of the memory cell to reduce the leakage current in the standby mode. Besides, a memory bank partition scheme and a clock gating scheme are also used to save more power. Finally, a fully different concept from current I/O designs is proposed. The novel I/O cell takes advantage of reducing output voltage swing as well as transistors with different threshold voltages such that the area and power consumption of overall chip can be drastically reduced.

The explosive growth of battery operated devices has made low-power design a priority in recent years. Moreover, embedded SRAM units have become an important block in modern SoCs. The increasing number of transistor count in the SRAM units and the surging leakage current of the MOS transistors in the scaled technologies have made the SRAM unit a power hungry block from both dynamic and static perspectives. Owing to high bitline voltage swing during write operation, the write power consumption is dominated the dynamic power consumption. The static power consumption is mainly due to the leakage current associated with the SRAM cells distributed in the array. Moreover, as supply voltage decreases to tackle the power consumption, the data stability of the SRAM cells have become a major concern in recent years. <br /><br /> To reduce the write power consumption, several schemes such as row based sense amplifying cell (SAC) and hierarchical bitline sense amplification (HBLSA) have been proposed. However, these schemes impose architectural limitations on the design in terms of the number of words on a row. Beside, the effectiveness of these methods is limited to the dynamic power consumption. Conventionally, reduction of the cell supply voltage and exploiting the body effect has been suggested to reduce the cell leakage current. However, variation of the supply voltage of the cell associates with a higher dynamic power consumption and reduced cell data stability. Conventionally qualified by Static Noise Margin (SNM), the ability of the cell to retain the data is reduced under a lower supply voltage conditions. <br /><br /> In this thesis, we revisit the concept of data stability from the dynamic perspective. A new criteria for the data stability of the SRAM cell is defined. The new criteria suggests that the access time and non-access time (recovery time) of the cell can influence the data stability in a SRAM cell. The speed vs. stability trade-off opens new opportunities for aggressive power reduction for low-power applications. Experimental results of a test chip implemented in a 130 <em>nm</em> CMOS technology confirmed the concept and opened a ground for introduction of a new operational mode for the SRAM cells. <br /><br /> We introduced a new architecture; Segmented Virtual Grounding (SVGND) to reduce the dynamic and static power reduction in SRAM units at the same time. Thanks to the new concept for the data stability in SRAM cells, we introduced the new operational mode of Accessed Retention Mode (AR-Mode) to the SRAM cell. In this mode, the accessed SRAM cell can retain the data, however, it does not discharge the bitline. The new architecture outperforms the recently reported low-power schemes in terms of dynamic power consumption, thanks to the exclusive discharge of the bitline and the cell virtual ground. In addition, the architecture reduces the leakage current significantly since it uses the back body biasing in both load and drive transistors. <br /><br /> A 40Kb SRAM unit based on SVGND architecture is implemented in a 130 <em>nm</em> CMOS technology. Experimental results exhibit a remarkable static and dynamic power reduction compared to the conventional and previously reported low-power schemes as expect from the simulation results.

The explosive growth of battery operated devices has made low-power design a priority in recent years. Moreover, embedded SRAM units have become an important block in modern SoCs. The increasing number of transistor count in the SRAM units and the surging leakage current of the MOS transistors in the scaled technologies have made the SRAM unit a power hungry block from both dynamic and static perspectives. Owing to high bitline voltage swing during write operation, the write power consumption is dominated the dynamic power consumption. The static power consumption is mainly due to the leakage current associated with the SRAM cells distributed in the array. Moreover, as supply voltage decreases to tackle the power consumption, the data stability of the SRAM cells have become a major concern in recent years. <br /><br /> To reduce the write power consumption, several schemes such as row based sense amplifying cell (SAC) and hierarchical bitline sense amplification (HBLSA) have been proposed. However, these schemes impose architectural limitations on the design in terms of the number of words on a row. Beside, the effectiveness of these methods is limited to the dynamic power consumption. Conventionally, reduction of the cell supply voltage and exploiting the body effect has been suggested to reduce the cell leakage current. However, variation of the supply voltage of the cell associates with a higher dynamic power consumption and reduced cell data stability. Conventionally qualified by Static Noise Margin (SNM), the ability of the cell to retain the data is reduced under a lower supply voltage conditions. <br /><br /> In this thesis, we revisit the concept of data stability from the dynamic perspective. A new criteria for the data stability of the SRAM cell is defined. The new criteria suggests that the access time and non-access time (recovery time) of the cell can influence the data stability in a SRAM cell. The speed vs. stability trade-off opens new opportunities for aggressive power reduction for low-power applications. Experimental results of a test chip implemented in a 130 <em>nm</em> CMOS technology confirmed the concept and opened a ground for introduction of a new operational mode for the SRAM cells. <br /><br /> We introduced a new architecture; Segmented Virtual Grounding (SVGND) to reduce the dynamic and static power reduction in SRAM units at the same time. Thanks to the new concept for the data stability in SRAM cells, we introduced the new operational mode of Accessed Retention Mode (AR-Mode) to the SRAM cell. In this mode, the accessed SRAM cell can retain the data, however, it does not discharge the bitline. The new architecture outperforms the recently reported low-power schemes in terms of dynamic power consumption, thanks to the exclusive discharge of the bitline and the cell virtual ground. In addition, the architecture reduces the leakage current significantly since it uses the back body biasing in both load and drive transistors. <br /><br /> A 40Kb SRAM unit based on SVGND architecture is implemented in a 130 <em>nm</em> CMOS technology. Experimental results exhibit a remarkable static and dynamic power reduction compared to the conventional and previously reported low-power schemes as expect from the simulation results.

Em nossos dias a crescente busca por portabilidade e desempenho resulta em esforços focados na maximização da duração de bateria dos equipamentos em fabricação, ou seja, busca-se a conflitante solução de circuitos com baixo consumo e ao mesmo tempo com alto desempenho. Neste contexto usualmente na composição de equipamentos portáteis empregam-se SOC´s (Systems On Chip) o que barateia o custo de produção e integração destes circuitos. SOC´s são sistemas completos que executam uma determinada função integrados em uma pastilha de silício única, normalmente possuem memórias SRAM como componente do sistema, que são utilizadas como memórias de alta performance e baixa latência e/ou também como caches. O grande desafio de projeto em memórias SRAMS é a relação de desempenho versus potência consumida a ser otimizada. Basicamente por sua construção estes circuitos apresentam alto consumo de potência, dinâmica e estática, relacionada a primeira diretamente ao aumento de freqüência de operação. Um dos focos desta dissertação é explorar soluções para a redução de consumo de energia tanto dinâmica como estática, sendo a redução de consumo estático de células de memória em standby buscando desempenho, estabilidade e baixo consumo de energia. No desenvolvimento de técnicas para projeto de circuitos analógicos em tecnologias nanométricas, os TST´s (T-Shaped Transistors – Transistor tipo T) surgem como dispositivos com características potenciais para projeto analógico de baixa potência. TSTs / TATs (Trapezoidal Associations of Transistors – Associação Trapezoidal de transistores) são estruturas self-cascode que podem tornar-se uma boa escolha por apresentar redução do leakage, redução na área utilizada e com incremento na regularidade do layout e no casamento entre transistores, propriedade importantíssima para circuitos analógicos. Sendo este o segundo foco deste texto através do estudo e análise das medidas elétricas dos TSTs executadas para comprovação das características destes dispositivos. Também apresenta-se uma análise das possibilidades de utilização dos TSTs em projeto analógico para tecnologias nanométricas. / Nowadays the increasing needs for portability and performance has resulted in efforts to increase battery life, i. e., the conflicting demands for low power consumption and high performance circuits. In this context using SOC´s (System On Chip) in the development for portable equipments composition, an integration of an entire system for a given function in a single silicon die will provide less production costs and less integration costs. SOC´s normally include a SRAM memory as its building block and are used to achieve memories with low latency and short access time or (and) as caches. A performance versus power consumption analysis of SRAM memory building blocks shows a great challenge to be solved. The electrical design aspects of these blocks reveal high power consumption, dynamic and static, and the former is directly proportional to the operating frequency. The design space exploration for dynamic and leakage consumption reduction in these circuits is one of the focus of this work. The main contribution of this topic is the leakage reduction techniques based in performance, stability and low energy consumption for the memory cell stand-by mode. Among the electrical techniques developed for analog circuits at the 20-100 nanometer scale, the TST (T-Shaped Transistors) rises with potential characteristics for analog low power design. TST /TAT (Trapezoidal Associations of Transistors) are selfcascode structures and can be turning into a good alternative for leakage and area reduction. Another point is the increment in mismatch and layout regularity, all these characteristics being very important in analog designs. The TST electrical measurements study and analysis are developed to show the device properties. An analysis of the TST desired properties and extrapolation for nanometer technologies analog design are also presented.

Em nossos dias a crescente busca por portabilidade e desempenho resulta em esforços focados na maximização da duração de bateria dos equipamentos em fabricação, ou seja, busca-se a conflitante solução de circuitos com baixo consumo e ao mesmo tempo com alto desempenho. Neste contexto usualmente na composição de equipamentos portáteis empregam-se SOC´s (Systems On Chip) o que barateia o custo de produção e integração destes circuitos. SOC´s são sistemas completos que executam uma determinada função integrados em uma pastilha de silício única, normalmente possuem memórias SRAM como componente do sistema, que são utilizadas como memórias de alta performance e baixa latência e/ou também como caches. O grande desafio de projeto em memórias SRAMS é a relação de desempenho versus potência consumida a ser otimizada. Basicamente por sua construção estes circuitos apresentam alto consumo de potência, dinâmica e estática, relacionada a primeira diretamente ao aumento de freqüência de operação. Um dos focos desta dissertação é explorar soluções para a redução de consumo de energia tanto dinâmica como estática, sendo a redução de consumo estático de células de memória em standby buscando desempenho, estabilidade e baixo consumo de energia. No desenvolvimento de técnicas para projeto de circuitos analógicos em tecnologias nanométricas, os TST´s (T-Shaped Transistors – Transistor tipo T) surgem como dispositivos com características potenciais para projeto analógico de baixa potência. TSTs / TATs (Trapezoidal Associations of Transistors – Associação Trapezoidal de transistores) são estruturas self-cascode que podem tornar-se uma boa escolha por apresentar redução do leakage, redução na área utilizada e com incremento na regularidade do layout e no casamento entre transistores, propriedade importantíssima para circuitos analógicos. Sendo este o segundo foco deste texto através do estudo e análise das medidas elétricas dos TSTs executadas para comprovação das características destes dispositivos. Também apresenta-se uma análise das possibilidades de utilização dos TSTs em projeto analógico para tecnologias nanométricas. / Nowadays the increasing needs for portability and performance has resulted in efforts to increase battery life, i. e., the conflicting demands for low power consumption and high performance circuits. In this context using SOC´s (System On Chip) in the development for portable equipments composition, an integration of an entire system for a given function in a single silicon die will provide less production costs and less integration costs. SOC´s normally include a SRAM memory as its building block and are used to achieve memories with low latency and short access time or (and) as caches. A performance versus power consumption analysis of SRAM memory building blocks shows a great challenge to be solved. The electrical design aspects of these blocks reveal high power consumption, dynamic and static, and the former is directly proportional to the operating frequency. The design space exploration for dynamic and leakage consumption reduction in these circuits is one of the focus of this work. The main contribution of this topic is the leakage reduction techniques based in performance, stability and low energy consumption for the memory cell stand-by mode. Among the electrical techniques developed for analog circuits at the 20-100 nanometer scale, the TST (T-Shaped Transistors) rises with potential characteristics for analog low power design. TST /TAT (Trapezoidal Associations of Transistors) are selfcascode structures and can be turning into a good alternative for leakage and area reduction. Another point is the increment in mismatch and layout regularity, all these characteristics being very important in analog designs. The TST electrical measurements study and analysis are developed to show the device properties. An analysis of the TST desired properties and extrapolation for nanometer technologies analog design are also presented.

Em nossos dias a crescente busca por portabilidade e desempenho resulta em esforços focados na maximização da duração de bateria dos equipamentos em fabricação, ou seja, busca-se a conflitante solução de circuitos com baixo consumo e ao mesmo tempo com alto desempenho. Neste contexto usualmente na composição de equipamentos portáteis empregam-se SOC´s (Systems On Chip) o que barateia o custo de produção e integração destes circuitos. SOC´s são sistemas completos que executam uma determinada função integrados em uma pastilha de silício única, normalmente possuem memórias SRAM como componente do sistema, que são utilizadas como memórias de alta performance e baixa latência e/ou também como caches. O grande desafio de projeto em memórias SRAMS é a relação de desempenho versus potência consumida a ser otimizada. Basicamente por sua construção estes circuitos apresentam alto consumo de potência, dinâmica e estática, relacionada a primeira diretamente ao aumento de freqüência de operação. Um dos focos desta dissertação é explorar soluções para a redução de consumo de energia tanto dinâmica como estática, sendo a redução de consumo estático de células de memória em standby buscando desempenho, estabilidade e baixo consumo de energia. No desenvolvimento de técnicas para projeto de circuitos analógicos em tecnologias nanométricas, os TST´s (T-Shaped Transistors – Transistor tipo T) surgem como dispositivos com características potenciais para projeto analógico de baixa potência. TSTs / TATs (Trapezoidal Associations of Transistors – Associação Trapezoidal de transistores) são estruturas self-cascode que podem tornar-se uma boa escolha por apresentar redução do leakage, redução na área utilizada e com incremento na regularidade do layout e no casamento entre transistores, propriedade importantíssima para circuitos analógicos. Sendo este o segundo foco deste texto através do estudo e análise das medidas elétricas dos TSTs executadas para comprovação das características destes dispositivos. Também apresenta-se uma análise das possibilidades de utilização dos TSTs em projeto analógico para tecnologias nanométricas. / Nowadays the increasing needs for portability and performance has resulted in efforts to increase battery life, i. e., the conflicting demands for low power consumption and high performance circuits. In this context using SOC´s (System On Chip) in the development for portable equipments composition, an integration of an entire system for a given function in a single silicon die will provide less production costs and less integration costs. SOC´s normally include a SRAM memory as its building block and are used to achieve memories with low latency and short access time or (and) as caches. A performance versus power consumption analysis of SRAM memory building blocks shows a great challenge to be solved. The electrical design aspects of these blocks reveal high power consumption, dynamic and static, and the former is directly proportional to the operating frequency. The design space exploration for dynamic and leakage consumption reduction in these circuits is one of the focus of this work. The main contribution of this topic is the leakage reduction techniques based in performance, stability and low energy consumption for the memory cell stand-by mode. Among the electrical techniques developed for analog circuits at the 20-100 nanometer scale, the TST (T-Shaped Transistors) rises with potential characteristics for analog low power design. TST /TAT (Trapezoidal Associations of Transistors) are selfcascode structures and can be turning into a good alternative for leakage and area reduction. Another point is the increment in mismatch and layout regularity, all these characteristics being very important in analog designs. The TST electrical measurements study and analysis are developed to show the device properties. An analysis of the TST desired properties and extrapolation for nanometer technologies analog design are also presented.

No description available.

The ever expanding range of applications for embedded systems continues to offer new challenges (and opportunities) to chip manufacturers. Applications ranging from exciting high resolution gaming to routine tasks like temperature control need to be supported on increasingly small devices with shrinking dimensions and tighter energy budgets. These systems benefit greatly by having the capability to operate over a wide range of supply voltages, known as ultra dynamic voltage scaling (U-DVS). This refers to systems capable of operating from nominal voltages down to sub-threshold voltages. Memories play an important role in these systems with future chips estimated to have over 80% of chip area occupied by memories. This thesis presents the design and characterization of an ultra dynamic voltage scalable memory (SRAM) that functions from nominal voltages down to sub-threshold voltages without the need for external support. The key contributions of the thesis are as follows: 1) A variation tolerant reference generation for single ended sensing: We present a reference generator, for U-DVS memories, that tracks the memory over a wide range of voltages and is tunable to allow functioning down to sub-threshold voltages. Replica columns are used to generate the reference voltage which allows the technique to track slow changes such as temperature and aging. A few configurable cells in the replica column are found to be sufficient to cover the whole range of voltages of interest. The use of tunable delay line to generate timing is shown to help in overcoming the effects of process variations. 2) Random-sampling based tuning algorithm: Tuning is necessary to overcome the in-creased effects of variation at lower voltages. We present an random-sampling based BIST tuning algorithm that significantly speed-up the tuning ensuring that the time required to tune is comparable to a single MBIST algorithm. Further, the use of redundancy after delay tuning enables maximum utilization of redundancy infrastructure to reduce power consumption and enhance performance. 3) Testing and Characterization for U-DVS systems: Testing and characterization is an important challenge in U-DVS systems that have remained largely unexplored. We propose an iterative technique that allows realization of an on-chip oscilloscope with minimal area overhead. The all digital nature of the technique makes it simple to design and implement across technology nodes. Combining the proposed techniques allows the designed 4 Kb SRAM array to function from 1.2 V down to 310 mV with reads functioning down to 190 mV. This would contribute towards moving ultra wide voltage operation a step closer towards implementation in commercial designs.