Atualmente, as tecnologias disponíveis para a fabricação de dispositivos eletrônicos permitem um alto grau de integração de semicondutores. Entretanto, esta integração torna o projeto, a verificação e o teste de circuitos integrados mais difíceis. Normalmente, o projeto de circuitos integrados é consideravelmente afetado com a diminuição do tamanho dos dispositivos eletrônicos em tecnologias sub-micrônicas. Conseqüentemente, os projetistas adotam metodologias rígidas para produzir circuitos de alta qualidade em tempo razoável. Ferramentas de auxílio ao projeto de circuitos eletrônicos são utilizadas para automatizar algumas das etapas do projeto, ajudando o projetista a encontrar boas soluções rapidamente. Uma das tarefas mais difíceis no projeto de circuitos integrados é fazer com que o circuito respeite as restrições de atraso. Isto depende de várias etapas do processo de síntese. Em metodologias baseadas em bibliotecas de células, isto está diretamente relacionado ao algoritmo para mapeamento tecnológico e as células disponíveis na biblioteca. O atraso de cada célula depende do tamanho dos transistores e da topologia da rede de transistores. Isso determina as características de atraso, potência e área de uma célula. O mapeamento tecnológico define as principais características estruturais do circuito, principalmente em área, potência e atraso. A qualidade do circuito mapeado depende das células disponíveis na biblioteca de células. Este trabalho propõe um novo método para mapeamento com bibliotecas virtuais para redução de atraso em circuitos combinacionais. Ambos os algoritmos baseiam-se em uma topologia de células capaz de implementar funções Booleanas com cadeias mínimas de transistores em série. Os algoritmos reduzem o número de transistores em série do caminho mais longo do circuito, considerando que cada célula é implementada por uma rede de transistores que obedecem um número máximo de transistores em série. O número de transistores em série é calculado de forma Booleana, garantindo que este seja o número mínimo necessário para implementar a função lógica da célula. Os algoritmos estão integrados a um gerador de células que utiliza tal topologia e realiza o dimensionamento dos transistores. Ganhos significativos podem ser obtidos combinando estas duas técnicas em uma ferramenta para mapeamento tecnológico. / Currently, microelectronic technologies enable high degrees of semiconductor integration. However, this integration makes the design, verification, and test challenges more difficult. The circuit design is often the first area under assault by the effects of aggressive scaling in deep-submicron technologies. Therefore, designers have adopted strict methodologies to deal with the challenge of developing high quality designs on a reasonable time. Electronic Design Automation tools play an important role, automating some of the design phases and helping the designer to find a good solution faster. One of the hardest challenges of an integrated circuit design is to meet the timing requirements. It depends on several steps of the synthesis flow. In standard cell based flows, it is directly related to the technology mapping algorithm and the cells available in the library. The performance of a cell is directly related to the transistor sizing and the cell topology. It determines the timing, power and area characteristics of a cell. Technology mapping has a major impact on the structure of the circuit, and on its delay and area characteristics. The quality of the mapped circuit depends on the richness of the cell library. This thesis proposes two different approaches for library-free technology mapping aiming delay reduction in combinational circuits. Both algorithms rely on a cell topology able to implement Boolean functions using minimal transistors stacks. They reduce the overall number of serial transistors through the longest path, considering that each transistor network of a cell has to obey to a maximum admitted chain. The mapping algorithms are integrated to a cell generator that creates cells with minimal transistor stacks. This cell generator is also in charge of performing the transistor sizing. Significant gains can be obtained in delay due to both aspects combined into the proposed mapping tool.

The processors and digital circuits designed today contain billions of transistors on a small piece of silicon. As devices are becoming smaller, slimmer, faster, and more efficient, the transistors also have to keep up with the demands and needs of the daily user. Unfortunately, the CMOS technology has reached its limit and cannot be used to scale down due to the transistor's breakdown caused by short channel effects. An alternative solution to this is the FinFET transistor technology, where the gate of the transistor is a three dimensional fin that surrounds the transistor and prevents the breakdown caused by scaling and short channel effects. FinFET devices are reported to have excellent control over short channel effects, high On/Off Ratio, extremely low gate leakage current and relative immunization over gate edge line roughness. Sub 20 nm node size is perceived to be the limit of scaling the CMOS transistors, but FinFETs can be scaled down further because of its unique design. Due to these advantages, the VLSI industry has now shifted to FinFET in implementation of their designs. However, these transistors have not been completely opened to academia. Analyzing and observing the effects of these devices can be pivotal in gaining an in-depth understanding of them. This thesis explores the implementation of FinFETs using a standard cell library designed using these transistors. The FinFET package file used to design these cells is a 15nm FinFET technology file developed by NCSU in collaboration with Cadence and Mentor Graphics. Post design, the cells were characterized, the results were analyzed and compared with cells designed using CMOS transistors at different node sizes to understand and extrapolate conclusions on FinFET devices.

Many modern digital systems use forms of CMOS logical implementation due to the straight forward design nature of CMOS logic and minimal device area since CMOS uses fewer transistors than other logic families. To achieve high-performance requirements in mixed-signal chip development and quiet, noiseless circuitry, this thesis provides an alternative toCMOSin the form of MOS Current Mode Logic (MCML). MCML dissipates constant current and does not produce noise during value changing in a circuit CMOS circuits do. CMOS logical networks switch during clock ticks and with every device switching, noise is created on the supply and ground to deal with the transitions. Creating a noiseless standard cell library with MCML allows use of circuitry that uses low voltage switching with 1.5V between logic levels in a quiet or mixed-signal environment as opposed to the full rail to rail swinging of CMOS logic. This allows cohesive implementation with analog circuitry on the same chip due to constant current and lower switching ranges not creating rail noise during digital switching. Standard cells allow for the Cadence tools to automatically generate circuits and Cadence serves as the development platform for the MCML standard cells. The theory surrounding MCML is examined along with current and future applications well-suited for MCML are researched and explored with the goal of highlighting valid candidate circuits for MCML. Inverters and NAND gates with varying current drives are developed to meet these specialized goals and are simulated to prove viability for quiet, mixed-signal applications. Analysis and results show that MCML is a superior implementation choice compared toCMOSfor high speed and mixed signal applications due to frequency independent power dissipation and lack of generated noise during operation. Noise results show rail current deviations of 50nA to 300nA during switching over an average operating current of 20µA to 80µA respectively. The multiple order of magnitude difference between noise and signal allow the MCML cells to dissipate constant power and thus perform with no noise added to a system. Additional simulated results of a 31-stage ring oscillator result in a frequency for MCML of 1.57GHz simulated versus the 150.35MHz that MOSIS tested on a fabricated 31-stage CMOS oscillator. The layouts designed for the standard cell library conform to existing On Semiconductor ami06 technology dimensions and allow for design of any logical function to be fabricated. The I/O signals of each cell operate at the same input and output voltage swings which allow seamless integration with each other for implementation in any logical configuration.