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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Analysis and Design of a Low Power 1.2V CMOS Downconversion Mixer Utilising Substrate Biasing / Substrate Biasing Techniques on Gilbert Mixer

Gon, Horace 10 1900 (has links)
This thesis presents detail theoretical analysis of downconversion Gilbert cell mixer with the improvements on major performance parameters by utilizing different substrate biasing techniques. By modifying the threshold voltage of the switching core, the LO transistors perform more ideally as a perfect switch. It improves the active mixer performances in conversion gain, noise and linearity performances. The techniques are implemented on a 1.2 V low power CMOS downconversion mixer for performance comparisons between simulation and measurements result. They are realized in TSMC 0.18 um CMOS technology. It shows that body-biasing techniques help to increase the switching efficiency of the Gilbert mixer. And a mixer with a better switching provides better performance. With no additional power consumption, the no body effect technique in Design B has shown a 1.5 dB higher in conversion gain, 2 dBm higher in IIP3, and a 0.5 dB lower in NF performance. With the varying biasing technique implemented in Design C, it shows an improvement of 22 dB in conversion gain. Both Design B and C have less than 2 mW power consumption and are suitable for Bluetooth applications. This thesis introduces a stage-by-stage procedure for designing a Gilbert mixer; design tradeoffs at each stage are also discussed. / Thesis / Master of Applied Science (MASc)
2

Reactive Sputter Deposition of Lithium Phosphorus Oxynitride Thin Films, A Li Battery Solid State Electrolyte

Mani, Prabhu Doss 01 January 2015 (has links)
Lithium phosphorus oxy-nitride (LiPON) thin films are widely studied and used as a thin film electrolyte for lithium ion battery applications. LiPON thin films may be prepared by many techniques, but RF sputter deposition is most frequently used and was investigated in this dissertation, in spite of its low deposition rate, because of it offers more reliable and controllable processing. This dissertation includes the methodologies of sputter deposition and materials characterization of the LiPON thin film electrolytes. The LiPON thin films were deposited under varying conditions of process gas, substrate bias, and deposition temperature. To understand the variations in ionic conductivity observed, the films were extensively characterized to examine structural and compositional differences, including examination by x-ray photoelectron spectroscopy (XPS), inductively coupled plasma optical emission spectroscopy (ICP/OES), and spectroscopic ellipsometry. In addition, film density, and the intrinsic stress of the deposited films were also studied. The highest ionic conductivity of 9.8 x 10-6 S/cm was obtained at elevated deposition temperature and is correlated to a reduced density of defects, as indicated from the optical characterization.
3

Low-frequency noise characterization, evaluation and modeling of advanced Si- and SiGe-based CMOS transistors

von Haartman, Martin January 2006 (has links)
A wide variety of novel complementary-metal-oxide-semiconductor (CMOS) devices that are strong contenders for future high-speed and low-noise RF circuits have been evaluated by means of static electrical measurements and low-frequency noise characterizations in this thesis. These novel field-effect transistors (FETs) include (i) compressively strained SiGe channel pMOSFETs, (ii) tensile strained Si nMOSFETs, (iii) MOSFETs with high-k gate dielectrics, (iv) metal gate and (v) silicon-on-insulator (SOI) devices. The low-frequency noise was comprehensively characterized for different types of operating conditions where the gate and bulk terminal voltages were varied. Detailed studies were made of the relationship between the 1/f noise and the device architecture, strain, device geometry, location of the conduction path, surface cleaning, gate oxide charges and traps, water vapour annealing, carrier mobility and other technological factors. The locations of the dominant noise sources as well as their physical mechanisms were investigated. Model parameters and physical properties were extracted and compared. Several important new insights and refinements of the existing 1/f noise theories and models were also suggested and analyzed. The continuing trend of miniaturizing device sizes and building devices with more advanced architectures and complex materials can lead to escalating 1/f noise levels, which degrades the signal-to-noise (SNR) ratio in electronic circuits. For example, the 1/f noise of some critical transistors in a radio receiver may ultimately limit the information capacity of the communication system. Therefore, analyzing electronic devices in order to control and find ways to diminish the 1/f noise is a very important and challenging research subject. We present compelling evidence that the 1/f noise is affected by the distance of the conduction channel from the gate oxide/semiconductor substrate interface, or alternatively the vertical electric field pushing the carriers towards the gate oxide. The location of the conduction channel can be varied by the voltage on the bulk and gate terminals as well by device engineering. Devices with a buried channel architecture such as buried SiGe channel pMOSFETs and accumulation mode MOSFETs on SOI show significantly reduced 1/f noise. The same observation is made when the substrate/source junction is forward biased which decreases the vertical electric field in the channel and increases the inversion layer separation from the gate oxide interface. A 1/f noise model based on mobility fluctuations originating from the scattering of electrons with phonons or surface roughness was proposed. Materials with a high dielectric constant (high-k) is necessary to replace the conventional SiO2 as gate dielectrics in the future in order to maintain a low leakage current at the same time as the capacitance of the gate dielectrics is scaled up. In this work, we have made some of the very first examinations of 1/f noise in MOSFETs with high-k structures composed by layers of HfO2, HfAlOx and Al2O3. The 1/f noise level was found to be elevated (up to 3 orders of magnitude) in the MOSFETs with high-k gate dielectrics compared to the reference devices with SiO2. The reason behind the higher 1/f noise is a high density of traps in the high-k stacks and increased mobility fluctuation noise, the latter possibly due to noise generation in the electron-phonon scattering that originates from remote phonon modes in the high-k. The combination of a TiN metal gate, HfAlOx and a compressively strained surface SiGe channel was found to be superior in terms of both high mobility and low 1/f noise. / QC 20100928

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